Jian Ming Jiang

US Patent:

6831510, Dec 14, 2004

Filed:

Feb 6, 2003

Appl. No.:

10/359893

Inventors:

Jian Hong Jiang - Sunnyvale CA

Assignee:

Fujitsu Limited - Kanagawa

International Classification:

H03F 136

US Classification:

330 85, 330310

Abstract:

A signal processing module provides high-gain amplification of received signals, while canceling some or all low-frequency error in the received signal. The signal processing module includes a multi-stage amplification series and a low-frequency error cancellation feedback loop.

US Patent:

6977600, Dec 20, 2005

Filed:

Apr 8, 2004

Appl. No.:

10/821034

Inventors:

Jian H. Jiang - Sunnyvale CA, US
Yasuo Hidaka - Santa Clara CA, US

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H03M001/00
G05F001/10

US Classification:

341136, 341156, 341172, 327540, 327538

Abstract:

A method for determining analog error of a signal includes receiving an input signal and sampling the input signal to generate a first sampled signal. The method also includes communicating the first sampled signal using a first communication path and a second communication path and sampling the first sampled signal from the first communication path to generate a second sampled signal. The method further includes converting the first sampled signal from the second communication path into a digital signal, storing the digital signal using a digital memory, comparing the second sampled signal to the digital signal, and determining an analog error of the input signal based on the comparison.

US Patent:

7002392, Feb 21, 2006

Filed:

Apr 8, 2004

Appl. No.:

10/821017

Inventors:

Jian H. Jiang - Sunnyvale CA, US

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H03L 5/00

US Classification:

327333

Abstract:

A method for converting a signal from a low voltage domain to a high voltage domain includes receiving an input signal in a low voltage domain, and using the input signal, controlling a first transistor having a first carrier type, a second transistor having a second carrier type different from the first carrier type, and a third transistor having the second carrier type to produce an output voltage at an output terminal. The first transistor is coupled to the output terminal and further coupled to a first voltage corresponding to a first value in a high voltage domain. The second and third transistors are coupled in series between the output terminal and a second voltage corresponding to a second value in the high voltage domain. The output voltage is selected to correspond to either the first voltage or the second voltage based upon the input signal.

US Patent:

7427878, Sep 23, 2008

Filed:

Jun 1, 2006

Appl. No.:

11/421522

Inventors:

Jian Hong Jiang - Sunnyvale CA, US
Yoichi Koyanagi - Saratoga CA, US

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H03K 19/0175
H03K 19/094

US Classification:

326 83, 326 82, 326 88

Abstract:

A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled programmable finger drives the signal and contributes to the capacitive loading of the driver, and a disabled programmable finger does not drive the signal and does not contribute to the capacitive loading of the driver.

US Patent:

7576567, Aug 18, 2009

Filed:

May 31, 2006

Appl. No.:

11/421239

Inventors:

Jian Hong Jiang - Sunnyvale CA, US

Assignee:

Fujitsu Limited - Kanagawa

International Classification:

H03K 19/094
H03K 19/20
H03K 19/086

US Classification:

326 83, 326112, 326115, 326121, 326127

Abstract:

A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

US Patent:

7579872, Aug 25, 2009

Filed:

May 31, 2006

Appl. No.:

11/421256

Inventors:

Jian Hong Jiang - Sunnyvale CA, US

Assignee:

Fujitsu Limited - Kanagawa

International Classification:

H03K 19/0175
H03K 19/094
H03K 19/20
H03K 19/086
H03K 3/00
H03B 1/00

US Classification:

326 83, 326 82, 326115, 326121, 326127, 327108

Abstract:

A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.

US Patent:

20140015543, Jan 16, 2014

Filed:

Jul 16, 2012

Appl. No.:

13/550181

Inventors:

Jian Hong JIANG - Los Altos CA, US

Assignee:

FUJITSU LIMITED - Kawasaki-shi

International Classification:

G01R 35/00

US Classification:

324601

Abstract:

A circuit configured to sample a signal of a source circuit and to provide calibration signals to a testing device of the signal sampled from the source circuit. The circuit may include an amplifier, a sampling circuit, and a calibration circuit. The amplifier may be configured to drive signals on an internal node to the testing device. The sampling circuit may be configured to provide a sample of a signal from the source circuit to the internal node. The calibration circuit may be configured to provide a first calibration signal and a second calibration signal to the internal node. The second calibration signal may be a known proportion of the first calibration signal.

US Patent:

20140016683, Jan 16, 2014

Filed:

Jul 16, 2012

Appl. No.:

13/550162

Inventors:

Jian Hong JIANG - Los Altos CA, US

Assignee:

FUJITSU LIMITED - Kawasaki-shi

International Classification:

H04B 1/38

US Classification:

375220

Abstract:

In an embodiment, a circuit may include an input node, an output node, an internal node, a compensation circuit, and an adjustable capacitance circuit. The compensation circuit may be configured to modify a return loss of a signal received at the input node. The compensation circuit may include a first inductive element, a second inductive element, and a capacitive element. The first inductive element may couple the input node and the output node. The second inductive element may couple the output node and the internal node. The capacitive element may couple the input node and the internal node. The adjustable capacitance circuit may be configured to adjustably modify the return loss of the signal received at the input node. The capacitance circuit may be coupled to the compensation circuit.