Jian Bin Liang

US Patent:

7584233, Sep 1, 2009

Filed:

Jun 28, 2005

Appl. No.:

11/170288

Inventors:

Christopher Edward Koob - Round Rock TX, US
Jian Liang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 7/00

US Classification:

708211

Abstract:

A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.

US Patent:

8384728, Feb 26, 2013

Filed:

Sep 14, 2007

Appl. No.:

11/855812

Inventors:

Guofang Jiao - San Diego CA, US
Jian Liang - San Diego CA, US
Chun Yu - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G09G 5/36

US Classification:

345557

Abstract:

Disclosed herein is a supplemental cache for use with a graphics processing unit. The supplemental cache can be used to supplement a vertex cache used with a graphics processing unit. The supplemental cache stores vertex values generated in assembling primitives from vertices provided to the graphics processing unit as part of an image geometry. Generated vertex values associated with a vertex determined to be shared by two or more primitives can be retrieved from the supplemental cache, so as to reduce the need to perform duplicative operations to generate vertex values for shared vertices.

US Patent:

20130205091, Aug 8, 2013

Filed:

Feb 2, 2012

Appl. No.:

13/364901

Inventors:

Jian Liang - San Diego CA, US
Chun Yu - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/08

US Classification:

711130, 711E12038

Abstract:

In general, this disclosure describes techniques for increasing the throughput of multi-bank cache memory systems accessible by multiple clients. Requests for data from a client may be stored in a pending buffer associated with the client for a first cache memory bank. For each of the requests for data, a determination may be made as to if the request is able to be fulfilled by a cache memory within the first cache memory bank regardless of a status of requests by the client for data at a second cache memory bank. Data requested from the cache memory by the client may be stored in a read data buffer associated with the client according to an order of receipt of the requests for data in the pending buffer.

US Patent:

20140040553, Feb 6, 2014

Filed:

Aug 2, 2012

Appl. No.:

13/565140

Inventors:

Jian Liang - San Diego CA, US
Jian Shen - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/08

US Classification:

711124, 711E12024

Abstract:

A method of transferring data between two caches comprises sending a first message from a first processor to a second processor indicating that data is available for transfer from a first cache associated with the first processor, requesting, from the second processor, a data transfer of the data from the first cache to a second cache associated with the second processor, transferring the data from the first cache to the second cache in response to the request, and sending a second message from the second processor to the first processor indicating that the data transfer is complete.

US Patent:

20200279347, Sep 3, 2020

Filed:

Mar 1, 2019

Appl. No.:

16/290761

Inventors:

- San Diego CA, US
Xuefeng TANG - San Diego CA, US
Jian LIANG - San Diego CA, US

International Classification:

G06T 1/20
G06T 1/60

Abstract:

The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.

US Patent:

20200273142, Aug 27, 2020

Filed:

Feb 21, 2019

Appl. No.:

16/282003

Inventors:

- San Diego CA, US
Tao Wang - Sunnyvale CA, US
Shangmei Yu - Sunnyvale CA, US
Jing Gao - San Jose CA, US
Jian Liang - San Diego CA, US
Andrew Evan Gruber - Arlington MA, US
Chun Yu - Rancho Santa Fe CA, US

International Classification:

G06T 1/60
G06F 3/06

Abstract:

The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.

US Patent:

20200027189, Jan 23, 2020

Filed:

Jul 23, 2018

Appl. No.:

16/042172

Inventors:

- San Diego CA, US
Andrew Yelder - New York NY, US
Jian Liang - San Diego CA, US
Avinash Seetharamaiah - San Diego CA, US

International Classification:

G06T 1/20
G06F 9/50
G06F 9/48

Abstract:

Methods, systems, and devices for dependency detection of a graphical processor unit (GPU) workload at a device are described. The method relates to generating a resource packet for a first GPU workload of a set of GPU workloads, the resource packet including a list of resources, identifying a first resource from the list of resources, retrieving a GPU address from a first memory location associated with the first resource, determining whether a dependency of the first resource exists between the first GPU workload and a second GPU workload from the set of GPU workloads based on the retrieving of the GPU address, and processing, when the dependency exists, the first resource after waiting for a duration to lapse.

US Patent:

20180189179, Jul 5, 2018

Filed:

Feb 3, 2017

Appl. No.:

15/423889

Inventors:

- San Diego CA, US
Jian Liang - San Diego CA, US
Fei Xu - San Jose CA, US
Zhen Chen - Saratoga CA, US
Chun Yu - Rancho Santa Fe CA, US
Tao Wang - Sunnyvale CA, US

International Classification:

G06F 12/0811
G06F 12/0875
G06F 12/0846

Abstract:

A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.