Jianjun S Wen from 2352 Oak Flat Rd, San Jose, CA 95131, age 54

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Location:

San Francisco, CA

Industry:

Computer Software

Work:

Trinet
Staff Engineer

Searching For Data Structures
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US Patent:

8612451, Dec 17, 2013
Filed:

Mar 31, 2011
Appl. No.:

13/076637
Inventors:

Jianjun Wen - San Jose CA, US
Xinyu Tang - Cupertino CA, US
Assignee:

Google Inc. - Mountain View CA
International Classification:

G06F 7/00
G06F 17/30
G06F 17/00
G06F 17/20
G06F 17/21
G06F 17/22
G06F 17/24
G06F 17/25
G06F 17/26
G06F 17/27
G06F 17/28
G06F 9/44
US Classification:

707741, 715209, 717125
Abstract:

A computer-implemented method includes receiving a request to search for a data structure associated with one or more search criteria; searching, an index in a data repository, for the data structure, with the search based on the one or more search criteria; identifying, based on searching, the data structure associated with the one or more search criteria; obtaining a definition for the data structure; generating an interface that when presented on a computing device renders a representation of the definition for the data structure; and sending the interface to the computing device associated with the request to search.

Hardware Architecture For Processing Data In Neural Network
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US Patent:

20210390381, Dec 16, 2021
Filed:

Aug 27, 2021
Appl. No.:

17/459782
Inventors:

Henry Verheyen - Marina CA, US
Jianjun Wen - San Jose CA, US
International Classification:

G06N 3/063
G06F 5/01
G06F 7/523
G06F 9/50
Abstract:

A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Hardware Architecture For Processing Data In Neural Network
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US Patent:

20210287075, Sep 16, 2021
Filed:

Mar 9, 2021
Appl. No.:

17/196922
Inventors:

Henry Verheyen - Marina CA, US
Jianjun Wen - San Jose CA, US
International Classification:

G06N 3/063
G06F 9/50
G06F 7/523
G06F 5/01
Abstract:

A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Time Series Analysis And Forecasting Using A Distributed Tournament Selection Process
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US Patent:

20200034745, Jan 30, 2020
Filed:

Aug 30, 2016
Appl. No.:

15/251244
Inventors:

- San Jose CA, US
Himanshu SHUKLA - San Jose CA, US
Cong LIU - Foster City, CA
Jianjun WEN - San Jose CA, US
Assignee:

Nutanix, Inc. - San Jose CA
International Classification:

G06N 99/00
G06N 5/02
Abstract:

A system for implementing seasonal time series analysis and forecasting using a distributed tournament selection process. Time series analysis is initiated by a prediction or runway event trigger. Prediction events include a determination of the availability of one or more resources at a given point in time or over a given time period. A runway event may include a determination of when a resource is below a minimum threshold level of availability. Training of the prediction models is based data taken from different time periods, accounting for any combination of time periods and/or for differing sampling frequencies or ranges. Processes for prosecuting a tournament to identify winning models are parallelized to achieve low latency tournament results. Ranking of each model and/or some combination of models is based on how precisely and/or conclusively the models match a determined set of training data.