Jingrong R Zhou from Vancouver, WA, age 70

Resumes

Jingrong Zhou

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Us Patents

Methods Of Quantifying Variations Resulting From Manufacturing-Induced Corner Rounding Of Various Features, And Structures For Testing Same
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US Patent:

7504270, Mar 17, 2009
Filed:

Jun 22, 2006
Appl. No.:

11/425913
Inventors:

David D. Wu - Austin TX, US
Mark W. Michael - Cedar Park TX, US
Akif Sultan - Austin TX, US
Jingrong Zhou - Austin TX, US
Assignee:

Advanced Micro Devices, Inc. - Austin TX
International Classification:

G10R 31/26
H01L 21/66
US Classification:

438 17, 438 14, 438 18, 257 48, 257E21521
Abstract:

The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Method Of Forming Transistor Devices With Different Threshold Voltages Using Halo Implant Shadowing
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US Patent:

7598161, Oct 6, 2009
Filed:

Sep 26, 2007
Appl. No.:

11/861534
Inventors:

Jingrong Zhou - Austin TX, US
Mark Michael - Cedar Park TX, US
Donna Michael, legal representative - Cedar Park TX, US
David Wu - Austin TX, US
James F. Buller - Austin TX, US
Akif Sultan - Austin TX, US
Assignee:

Advanced Micro Devices, Inc. - Austin TX
International Classification:

H01L 21/425
US Classification:

438527, 438531, 438514, 438 13, 257E21023
Abstract:

The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Soi Device With Charging Protection And Methods Of Making Same
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US Patent:

7727835, Jun 1, 2010
Filed:

Aug 19, 2008
Appl. No.:

12/194006
Inventors:

David D. Wu - Austin TX, US
Jingrong Zhou - Austin TX, US
Assignee:

Advanced Micro Devices, Inc. - Austin TX
International Classification:

H01L 21/00
US Classification:

438238, 438257, 438283, 438454, 257E21614, 257E21663, 257E21703, 257E29275, 257E29276
Abstract:

The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

Method For Fabricating A Semiconductor Device Having An Extended Stress Liner
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US Patent:

7761838, Jul 20, 2010
Filed:

Sep 26, 2007
Appl. No.:

11/861492
Inventors:

Zhonghai Shi - Austin TX, US
Mark Michael - Cedar Park TX, US
Donna Michael, legal representative - Cedar Park TX, US
David Wu - Austin TX, US
James F. Buller - Austin TX, US
Jingrong Zhou - Austin TX, US
Akif Sultan - Austin TX, US
Assignee:

Globalfoundries Inc. - Grand Cayman
International Classification:

G06F 17/50
H01L 21/8238
US Classification:

716 19, 716 21, 438199
Abstract:

The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Compensating For Layout Dimension Effects In Semiconductor Device Modeling
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US Patent:

7793240, Sep 7, 2010
Filed:

Sep 29, 2006
Appl. No.:

11/537390
Inventors:

Akif Sultan - Austin TX, US
Jian Chen - Austin TX, US
Mark W. Michael - Cedar Park TX, US
Jingrong R. Zhou - Austin TX, US
Assignee:

Advanced Micro Devices, Inc. - Austin TX
International Classification:

G06F 17/50
US Classification:

716 4, 716 5, 716 11
Abstract:

A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Method Of Forming Multiple Fins For A Semiconductor Device
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US Patent:

8003466, Aug 23, 2011
Filed:

Apr 8, 2008
Appl. No.:

12/099726
Inventors:

Zhonghai Shi - Austin TX, US
David Wu - Austin TX, US
Jingrong Zhou - Austin TX, US
Ruigang Li - Austin TX, US
Assignee:

Advanced Micro Devices, Inc. - Austin TX
International Classification:

H01L 21/336
H01L 21/00
H01L 21/84
H01L 21/338
H01L 21/8234
H01L 21/3205
H01L 21/4763
H01L 27/148
H01L 29/66
H01L 29/76
H01L 21/12
H01L 27/088
US Classification:

438283, 438149, 438157, 438176, 438197, 438585, 438587, 257241, 257287, 257288, 257347, 257401
Abstract:

A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

Method Of Fabricating Semiconductor Transistor Devices With Asymmetric Extension And/Or Halo Implants
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US Patent:

8026142, Sep 27, 2011
Filed:

May 8, 2009
Appl. No.:

12/463221
Inventors:

Zhonghai Shi - Austin TX, US
Jingrong Zhou - Austin TX, US
Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:

H01L 21/00
US Classification:

438279, 438286, 438302
Abstract:

A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

Charging Protection Device
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US Patent:

8048753, Nov 1, 2011
Filed:

Jun 12, 2009
Appl. No.:

12/483737
Inventors:

Jingrong Zhou - Austin TX, US
David Wu - Austin TX, US
James F. Buller - Austin TX, US
Assignee:

Globalfoundries Inc. - Grand Cayman
International Classification:

H01L 21/331
H01L 21/8222
US Classification:

438311, 438 9, 438199, 438141, 438753, 257E21042, 257E21051, 257E2132, 257E21311, 257E21352, 257E2137, 257E2155, 257E21546
Abstract:

Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P-doped substrate contact in the bulk silicon layer of the SOI substrate.