John W Rodgers

US Patent:

6448576, Sep 10, 2002

Filed:

Aug 30, 2001

Appl. No.:

09/943178

Inventors:

John D. Davis - Manassas VA
Thomas J. McIntyre - Nokesville VA
John C. Rodgers - Fairfax VA
Keith K. Sturcken - Nokesville VA
Peter W. Spreen - Fairfax VA
Tushar K. Shah - Columbia MD

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L 2904

US Classification:

257 50, 257529, 438132, 438601

Abstract:

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

US Patent:

6692994, Feb 17, 2004

Filed:

Jun 26, 2002

Appl. No.:

10/180645

Inventors:

John D. Davis - Manassas VA
Thomas J. McIntyre - Nokesville VA
John C. Rodgers - Fairfax VA
Keith K. Sturcken - Nokesville VA
Peter W. Spreen - Fairfax VA
Tushar K. Shah - Columbia MD

Assignee:

BAE Systems, Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L 2182

US Classification:

438128, 438204, 438132, 438622, 257 50

Abstract:

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

US Patent:

6750085, Jun 15, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331850

Inventors:

John C. Rodgers - Fairfax VA 22032
Jon D. Maimon - Manassas VA 20112

International Classification:

H01L 2100

US Classification:

438133, 438 95, 438102, 438629, 438639

Abstract:

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

US Patent:

6815266, Nov 9, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331850

Inventors:

John C. Rodgers - Fairfax VA
Jon D. Maimon - Manassas VA

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH
Ovonyx, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438133, 438 95, 438102, 438629, 438639

Abstract:

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

US Patent:

6909107, Jun 21, 2005

Filed:

Apr 26, 2004

Appl. No.:

10/831785

Inventors:

John C. Rodgers - Fairfax VA, US
Jon D. Maimon - Manassas VA, US

Assignee:

BAE Systems, Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L047/00
H01L021/00
H01L021/06
H01L021/332

US Classification:

257 3, 257 4, 438 95, 438102, 438133

Abstract:

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

US Patent:

7045383, May 16, 2006

Filed:

Mar 24, 2003

Appl. No.:

10/396587

Inventors:

Jon Maimon - Manassas VA, US
John Rodgers - Fairfax VA, US

Assignee:

BAE Systems Information and Ovonyx, Inc - Rochester Hills MI
Electronic Systems Integration Inc. - Nashua NH

International Classification:

H01L 21/00

US Classification:

438 95, 438637, 438640

Abstract:

A method for making a tapered opening. The defined tapered opening is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.

US Patent:

7337160, Feb 26, 2008

Filed:

Aug 12, 2004

Appl. No.:

10/918814

Inventors:

Joseph R. Marshall - Manassas VA, US
Richard W. Berger - Woodbridge VA, US
John C. Rodgers - Fairfax VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G06N 5/00

US Classification:

706 62, 706 45

Abstract:

Chalcogenide technology is used for radiation hardening for spaceborne systems and more particularly in C-RAM form for processors, field programmable gate arrays, startup RAMs, shadow storage and single-chip systems to protect these units.

US Patent:

7965541, Jun 21, 2011

Filed:

Nov 25, 2008

Appl. No.:

12/525458

Inventors:

Bin Li - Chantilly VA, US
John C. Rodgers - Fairfax VA, US
Nadim F. Haddad - Oakton VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
Ovonyx, Inc. - Rochester Hills MI

International Classification:

G11C 11/00

US Classification:

365156, 365154, 365163

Abstract:

A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.