John B Rodgers

US Patent:

6448576, Sep 10, 2002

Filed:

Aug 30, 2001

Appl. No.:

09/943178

Inventors:

John D. Davis - Manassas VA
Thomas J. McIntyre - Nokesville VA
John C. Rodgers - Fairfax VA
Keith K. Sturcken - Nokesville VA
Peter W. Spreen - Fairfax VA
Tushar K. Shah - Columbia MD

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L 2904

US Classification:

257 50, 257529, 438132, 438601

Abstract:

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

US Patent:

6555411, Apr 29, 2003

Filed:

Dec 18, 2001

Appl. No.:

10/024831

Inventors:

Zhenan Bao - Jersey City NJ
Edwin Arthur Chandross - Murray Hill NJ
John A. Rodgers - New Providence NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 540

US Classification:

438 99, 438197, 438158, 438199

Abstract:

The specification describes thin film transistor (TFT) devices with source/drain contacts made by a metallo organic deposition (MOD) method wherein a metallo organic compound/metal particulate mixture is deposited to form a base pattern, and the base pattern is then plated with gold. The porous, relatively high resistance base pattern is thereby converted to a corrosion resistant, low resistance contact. The plating covers the sidewalls of the base pattern, thus allowing the final channel length to be less than the minimum design rule used for depositing the base pattern.

US Patent:

6596569, Jul 22, 2003

Filed:

Mar 15, 2002

Appl. No.:

10/098201

Inventors:

Zhenan Bao - North Plainfield NJ
Peter Kian-Hoon Ho - North Plainfield NJ
Yueh-Lin Loo - Princeton NJ
John A. Rodgers - New Providence NJ
Takao Someya - New Providence NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 2100

US Classification:

438151, 438149, 438459, 438778

Abstract:

The specification describes a lamination method for thin film transistor TFT devices wherein each ply of the laminate is a polymer and each contains a portion of the TFT or the interconnection circuit. The plies are laminated together using a solid adhesive polymer layer on the surface of one or both of the plies. The solid adhesive polymer layer has a low elastic modulus that provides effective encapsulation of the TFT, and laminates the plies without high heat or pressure.

US Patent:

6692994, Feb 17, 2004

Filed:

Jun 26, 2002

Appl. No.:

10/180645

Inventors:

John D. Davis - Manassas VA
Thomas J. McIntyre - Nokesville VA
John C. Rodgers - Fairfax VA
Keith K. Sturcken - Nokesville VA
Peter W. Spreen - Fairfax VA
Tushar K. Shah - Columbia MD

Assignee:

BAE Systems, Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L 2182

US Classification:

438128, 438204, 438132, 438622, 257 50

Abstract:

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

US Patent:

6750085, Jun 15, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331850

Inventors:

John C. Rodgers - Fairfax VA 22032
Jon D. Maimon - Manassas VA 20112

International Classification:

H01L 2100

US Classification:

438133, 438 95, 438102, 438629, 438639

Abstract:

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

US Patent:

6815266, Nov 9, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331850

Inventors:

John C. Rodgers - Fairfax VA
Jon D. Maimon - Manassas VA

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH
Ovonyx, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438133, 438 95, 438102, 438629, 438639

Abstract:

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

US Patent:

6909107, Jun 21, 2005

Filed:

Apr 26, 2004

Appl. No.:

10/831785

Inventors:

John C. Rodgers - Fairfax VA, US
Jon D. Maimon - Manassas VA, US

Assignee:

BAE Systems, Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

H01L047/00
H01L021/00
H01L021/06
H01L021/332

US Classification:

257 3, 257 4, 438 95, 438102, 438133

Abstract:

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

US Patent:

7045383, May 16, 2006

Filed:

Mar 24, 2003

Appl. No.:

10/396587

Inventors:

Jon Maimon - Manassas VA, US
John Rodgers - Fairfax VA, US

Assignee:

BAE Systems Information and Ovonyx, Inc - Rochester Hills MI
Electronic Systems Integration Inc. - Nashua NH

International Classification:

H01L 21/00

US Classification:

438 95, 438637, 438640

Abstract:

A method for making a tapered opening. The defined tapered opening is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.