Joseph L Huang

US Patent:

6335636, Jan 1, 2002

Filed:

May 1, 2001

Appl. No.:

09/846409

Inventors:

Wayne Yeung - San Francisco CA
Chiakang Sung - Milpitas CA
Myron W. Wong - Fremont CA
Khai Nguyen - San Jose CA
Bonnie I. Wang - Cupertino CA
Xiaobao Wang - Santa Clara CA
Joseph Huang - San Jose CA
Im Whan Kim - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 38, 710103

Abstract:

A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

US Patent:

6346827, Feb 12, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/366937

Inventors:

Wayne Yeung - San Francisco CA
Chiakang Sung - Milpitas CA
Myron W. Wong - Fremont CA
Khai Nguyen - San Jose CA
Bonnie I. Wang - Cupertino CA
Xiaobao Wang - Santa Clara CA
Joseph Huang - San Jose CA
In Whan Kim - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 50, 326 45

Abstract:

A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

US Patent:

6366121, Apr 2, 2002

Filed:

May 25, 2001

Appl. No.:

09/865227

Inventors:

Richard G. Cliff - Milpitas CA
Francis B. Heile - Santa Clara CA
Joseph Huang - San Jose CA
Christopher F. Lane - Campbell CA
Fung Fung Lee - Milpitas CA
Cameron McClintock - Mountain View CA
David W. Mendel - Sunnyvale CA
Ninh D. Ngo - San Jose CA
Bruce B. Pedersen - San Jose CA
Srinivas T. Reddy - Fremont CA
Chiakang Sung - Milpitas CA
Kerry Veenstra - San Jose CA
Bonnie I. Wang - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 738

US Classification:

326 41, 326 39

Abstract:

A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e. g. , by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate âlonely registerâ function in modules of the regions.

US Patent:

6369624, Apr 9, 2002

Filed:

Nov 2, 1999

Appl. No.:

09/432142

Inventors:

Bonnie I. Wang - Cupertino CA
Joseph Huang - San Jose CA
Chiakang Sung - Milpitas CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Wayne Yeung - San Francisco CA
Khai Nguyen - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 706

US Classification:

327156, 327147, 327150, 327159, 331 25, 331 60

Abstract:

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

US Patent:

6384629, May 7, 2002

Filed:

Dec 15, 2000

Appl. No.:

09/738403

Inventors:

Joseph Huang - San Jose CA
Chiakang Sung - Milpitas CA
Bonnie I. Wang - Cupertino CA
Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
Richard G. Cliff - Milpitas CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 38, 326 40

Abstract:

An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

US Patent:

6392438, May 21, 2002

Filed:

Oct 6, 2000

Appl. No.:

09/684148

Inventors:

Richard G. Cliff - Milpitas CA
Srinivas T. Reddy - Santa Clara CA
David Edward Jefferson - San Jose CA
Rina Raman - Fremont CA
L. Todd Cope - San Jose CA
Christopher F. Lane - Campbell CA
Joseph Huang - San Jose CA
Francis B. Heile - Santa Clara CA
Bruce B. Pedersen - San Jose CA
David Wolk Mendel - Sunnyvale CA
Craig Schilling Lytle - Mountain View CA
Robert Richard Noel Bielby - Pleasonton CA
Kerry Veenstra - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 1977

US Classification:

326 41, 326 39

Abstract:

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

US Patent:

6400598, Jun 4, 2002

Filed:

Apr 25, 2001

Appl. No.:

09/843299

Inventors:

Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Chiakang Sung - Milpitas CA
Richard G. Cliff - Milpitas CA
Joseph Huang - San Jose CA
Bonnie I. Wang - Cupertino CA
Wayne Yeung - San Francisco CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 506

US Classification:

365 63, 326 39

Abstract:

A programmable logic device is equipped for low voltage differential signaling (âLVDSâ) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

US Patent:

6421812, Jul 16, 2002

Filed:

Jun 9, 1998

Appl. No.:

09/094186

Inventors:

Xiaobao Wang - Santa Clara CA
Chiakang Sung - Milpitas CA
Joseph Huang - San Jose CA
Bonnie Wang - Cupertino CA
Khai Nguyen - San Jose CA
Richard G. Cliff - Milpitas CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 5

Abstract:

A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register ( ) may be used to replace the programming mode select pins ( ) in a programmable logic device (PLD).