Le Thi Nguyen

US Patent:

6401194, Jun 4, 2002

Filed:

Jan 28, 1997

Appl. No.:

08/790142

Inventors:

Le Trong Nguyen - Monte Sereno CA
Heonchul Park - Cupertino CA
Roney S. Wong - Sunnyvale CA
Ted Nguyen - Saratoga CA
Edward H. Yu - Newark CA

Assignee:

Samsung Electronics Co., Ltd. - Seoul

International Classification:

G06F 9302

US Classification:

712210, 712212, 712 7, 712 8, 712 9, 712 4, 708507, 708524, 708682, 708550, 710 65, 710 66, 710127, 710 50

Abstract:

A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

US Patent:

6401232, Jun 4, 2002

Filed:

Jun 27, 2000

Appl. No.:

09/604419

Inventors:

Kevin R. Iadonato - San Jose CA
Le Trong Nguyen - Monte Sereno CA

Assignee:

Seiko Epson Corporation - Tokyo

International Classification:

G06F 1750

US Classification:

716 10, 712 26, 712201, 326 47, 326101, 327565

Abstract:

An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

US Patent:

6405273, Jun 11, 2002

Filed:

Nov 13, 1998

Appl. No.:

09/192170

Inventors:

Rod G. Fleck - Mountain View CA
Klaus Oberlaender - San Jose CA
Gigy Baror - Ramat Gan, IL
Alfred Eder - Friedberg, DE
Le Trong Nguyen - Monte Sereno CA

Assignee:

Infineon Technologies North America Corp. - San Jose CA

International Classification:

G06F 1300

US Classification:

710131

Abstract:

A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

US Patent:

6425054, Jul 23, 2002

Filed:

Oct 10, 2000

Appl. No.:

09/685982

Inventors:

Le Trong Nguyen - Monte Sereno CA

Assignee:

Samsung Electronics Co., Ltd. - Kyungki-do

International Classification:

G06F 1208

US Classification:

711117, 711118

Abstract:

To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem provides caching and data routing for the processors and buses. Multiple simultaneous communication paths can be used in the cache subsystem for the processors and buses. Furthermore, simultaneous reads and writes are supported to a cache memory in the cache subsystem.

US Patent:

6611908, Aug 26, 2003

Filed:

Jun 21, 2001

Appl. No.:

09/884943

Inventors:

Derek J. Lentz - Los Gatos CA
Yasuaki Hagiwara - Santa Clara CA
Te-Li Lau - Palo Alto CA
Cheng-Long Tang - San Jose CA
Le Trong Nguyen - Monte Sereno CA

Assignee:

Seiko Epson Corporation - Tokyo

International Classification:

G06F 1314

US Classification:

712 29, 710243, 710317

Abstract:

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

US Patent:

6647485, Nov 11, 2003

Filed:

May 10, 2001

Appl. No.:

09/852293

Inventors:

Le Trong Nguyen - Monte Sereno CA
Derek J. Lentz - Los Gatos CA
Yoshiyuki Miyayama - Santa Clara CA
Sanjiv Garg - Freemont CA
Yasuaki Hagiwara - Santa Clara CA
Johannes Wang - Redwood City CA
Te-Li Lau - Palo Alto CA
Quang H. Trang - San Jose CA

Assignee:

Seiko Epson Corporation - Tokyo

International Classification:

G06F 930

US Classification:

712 23, 712206, 712207, 712245, 712219, 711169

Abstract:

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

US Patent:

6782521, Aug 24, 2004

Filed:

May 7, 2002

Appl. No.:

10/139318

Inventors:

Kevin R. Iadonato - San Jose CA
Le Trong Nguyen - Monte Sereno CA

Assignee:

Seiko Epson Corporation - Tokyo

International Classification:

G06F 1750

US Classification:

716 10, 716 14, 716 7, 326 47, 326101, 327565, 712 26, 712201

Abstract:

An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

US Patent:

6915412, Jul 5, 2005

Filed:

Oct 30, 2002

Appl. No.:

10/283106

Inventors:

Le Trong Nguyen - Monte Sereno CA, US
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US

Assignee:

Seiko Epson Corporation - Tokyo

International Classification:

G06F015/76
G06F013/40
G06F009/38
G06F013/36

US Classification:

712 23, 712206, 712207, 712215, 712213, 712233, 712237, 712238, 712248, 712 41, 711125, 710 52, 710310

Abstract:

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.