Dr. Jiang graduated from the University of Maryland School of Medicine in 2009. He works in Los Angeles, CA and specializes in Ophthalmology. Dr. Jiang is affiliated with San Gabriel Valley Medical Center.
California Cardiovascular Consultants & Medical AssociatesCalifornia Cardiovascular Consultants 2333 Mowry Ave STE 300, Fremont, CA 94538 (510)7960222 (phone), (510)7967760 (fax)
Languages:
Arabic Chinese English Spanish Tagalog Vietnamese
Description:
Ms. Jiang works in Fremont, CA and specializes in Cardiovascular Disease. Ms. Jiang is affiliated with Eden Medical Center, Saint Rose Hospital, Seton Medical Center and Washington Hospital.
Lei Jiang - Camas WA, US Sadasivan Shankar - Cupertino CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F017/50
US Classification:
716 6, 716 5, 716 19, 716 20
Abstract:
An efficient TCAD tool to analyze the variation of topography and thickness of interconnects and components of integrated circuits introduced by multiple-layer chemical-mechanical planarization (CMP). Contact stress distribution is determined on all scales as a function of topography. A formulation is used relating the pad deformation and therefore stress directly to pattern topography ({d}), and the pad mechanical properties. The 3-dimensional stress and deformation field is described, along with representation of the statistical pad roughness and slurry thickness information. These process conditions are also functions of the surface topography and contact regimes. The stress-topography relationship is represented as [A]{P}={d}, where [A] is the influence coefficient matrix determined by the contact mechanics, and {P} and {d} represent local stress and topography on patterns. With given initial topography and slurry rate kinetics, the surface evolution at each time step of CMP can be traced iteratively to obtain post-CMP topography.
Lei Jiang - Aloha OR, US Sadasivan Shankar - Cupertino CA, US Paul Fischer - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B24B009/00
US Classification:
451 28, 451 54, 451 41
Abstract:
A method is provided for creating a polish pad. This may involve determining a design layout of a wafer. The design layout may include a distribution of metal line features on the wafer. A polish pad design may be created/determined based on the determined layer. The polish pad may have asperities having a width greater than a width of metal line features of the wafer.
Lei Jiang - Camas WA, US Jin Liu - Albuquerque NM, US Sadasivan Shankar - Cupertino CA, US Thomas Bramblett - Banks OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B24B001/00
US Classification:
451 60, 451444, 451446
Abstract:
An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.
Lei Jiang - Camas WA, US Jin Liu - Albuquerque NM, US Sadasivan Shankar - Cupertino CA, US Thomas Bramblett - Banks OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B24B 1/00
US Classification:
451 60, 451444, 451446
Abstract:
An apparatus for polishing a wafer comprising a rotatable polishing pad having a center of rotation and a rinse delivery conduit positioned adjacent to the polishing pad and substantially in radial alignment with the center. The rinse delivery conduit includes a plurality of nozzles to dispense a rinsing liquid. In one embodiment, the plurality of nozzles are configured and positioned to generate a higher flow rate of the rinsing liquid at the end of the rinse delivery conduit proximate to the center than at the end of the rinse delivery conduit distal to the center. In another embodiment, the rinse delivery conduit has a proximal end which is substantially adjacent the center and the distal end which is approximately adjacent an outer periphery of the pad.
Ultrasonic Electropolishing Of Conductive Material
Tatyana N. Andryushchenko - Portland OR, US Radek P. Chalupa - Hillsboro OR, US Anne E. Miller - Portland OR, US Lei Jiang - Camas WA, US
International Classification:
H01L 21/44 C25D 17/00
US Classification:
438653, 204194, 257E2104
Abstract:
In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while ultrasonically agitating the semiconductor wafer until a predetermined amount of the conductive layer remains over the barrier layer. Other embodiments are described and claimed.
Thermal Management Structures In Semiconductor Devices And Methods Of Fabrication
- Santa Clara CA, US Lei Jiang - Camas WA, US Colin Landon - Portland OR, US Daniel Pantuso - Portland OR, US Edwin Ramayya - Hillsboro OR, US Jeffrey Hicks - Banks OR, US Mehmet Koker Aykol - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/538 H01L 23/36
Abstract:
A device structure includes a first interconnect layer, a second interconnect layer, a device layer including a comprising a plurality of devices, where the device layer is between the first interconnect layer and the second interconnect layer. The device structure further includes a dielectric layer adjacent the second interconnect layer, where the dielectric layer includes one or more of metallic dopants or a plurality of metal structures, wherein the plurality of metal structures is electrically isolated from interconnect structures but in contact with a dielectric material of the second interconnect layer, and where the individual ones of the plurality of metal structures is above a region including at least some of the plurality of devices. The device structure further includes a substrate adjacent to the dielectric layer and a heat sink coupled with the substrate.