Oath
Senior Research Engineer
Yahoo
Research Engineer
Utah State University
Graduate Teaching Assistant
Yahoo May 2015 - Jul 2015
Summer Intern
Canon Usa May 2014 - Dec 2014
Senior Research Intern
Education:
Utah State University 2011 - 2015
Doctorates, Doctor of Philosophy, Computer Science
Kansas State University 2011
Master of Science, Masters
Kansas State University 2008 - 2011
Masters, Statistics
Emporia State University 2005 - 2008
Bachelors, Bachelor of Science, Economics
Skills:
Machine Learning Data Mining R Java Statistics Python Computer Science Matlab Image Processing Sql Data Analysis Computer Vision Artificial Intelligence Deep Learning Latex Teaching Software Engineering Sas C# Research Mathematics .Net Perl C++ Language Regression Planning Bayesian Networks Face Recognition Object Detection Classification Json Economics Gui Object Tracking Regression Analysis Amazon Web Services Batch Programming Applied Mathematics Databases
Futurewei Technologies
Head of Ic Lab
Department of Risk Management and Insurance Gsu
Thomas P Bowles Chair Professor of Actuarial Science
Huawei Technologies
Senior Director, Technical Planning and Strategy, Ic Lab
Intel Corporation Oct 2008 - Jun 2014
Platform Architect
Chinese American Semiconductor Professional Association Oct 2008 - Jun 2014
Advisor , Chairman and President Board Director
Education:
Cornell University 1991 - 1998
Doctorates, Doctor of Philosophy, Computer Graphics
Peking University 1987 - 1991
Bachelors, Bachelor of Science, Astrophysics
Erasmus University Rotterdam
Skills:
Semiconductors Asic Soc Ic Computer Architecture Embedded Systems Simulations Algorithms Circuit Design Product Management System Architecture Fpga Leadership Serdes Perl Eda Debugging Processors Cross Functional Team Leadership High Performance Computing Embedded Software Operational Execution Mixed Signal Team Leadership Strategic Leadership Hardware Architecture 3D Computer Graphics Algorithm Engineering Management R&D Software Engineering Technical Leadership Image Processing Signal Processing Distributed Systems Visionary Thinking C/C++/Systemc
Interests:
Christianity Kids Investing Sweepstakes Nascar Electronics Home Improvement Sports Golf Family Values Collecting Home Decoration
Walter E. Donovan - Milpitas CA Liang Peng - Sunnyvale CA
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 1500
US Classification:
345422
Abstract:
A system, method and article of manufacture are provided for shadow mapping while rendering a primitive in a graphics pipeline. Initially, an offset operation is performed in order to generate a depth value while rendering a primitive. Further, a value of a slope associated with an edge of the primitive is identified. Thereafter, the depth value is conditionally clamped based on the value of the slope.
System, Method And Article Of Manufacture For Shadow Mapping
Walter E. Donovan - Milpitas CA Liang Peng - Sunnyvale CA
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 1500
US Classification:
345426
Abstract:
A system, method and article of manufacture are provided for shadow mapping while rendering a primitive in a graphics pipeline. Initially, an offset operation is performed in order to generate a depth value while rendering a primitive. Further, a value of a slope associated with an edge of the primitive is identified. Thereafter, the depth value is conditionally clamped based on the value of the slope.
System, Method And Article Of Manufacture For Shadow Mapping
Walter E. Donovan - Milpitas CA, US Liang Peng - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 15/00
US Classification:
345426
Abstract:
A system, method and article of manufacture are provided for shadow mapping while rendering a primitive in a graphics pipeline. Initially, an offset operation is performed in order to generate a depth value while rendering a primitive. Further, a value of a slope associated with an edge of the primitive is identified. Thereafter, the depth value is conditionally clamped based on the value of the slope.
Atomic-Operation Coalescing Technique In Multi-Chip Systems
Qi Lin - Los Altos Hills CA, US Liang Peng - San Jose CA, US Craig E. Hampel - Los Altos CA, US Thomas J. Sheffler - San Francisco CA, US Steven C. Woo - Saratoga CA, US Bohuslav Rychlik - San Diego CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
G06F 13/00
US Classification:
711121, 711124, 711141, 711E12023, 712 32
Abstract:
A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
Digital Signal Processing Structure For Decoding Multiple Video Standards
In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.
Two Pass Architecture For H.264 Cabac Decoding Process
Liang Peng - San Jose CA, US Ankur Shah - Sunnyvale CA, US
International Classification:
H04N 7/12 H04N 11/04 H04N 11/02 H04B 1/66
US Classification:
375240260, 375240250, 375240240
Abstract:
An architecture capable of stream parsing of the H.264 Content Based Adaptive Binary Arithmetic Coding (CABAC) format is disclosed. The architecture employs a two pass dataflow approach to implement the functions of CABAC bit parsing and decoding processes (based on the H.264 CABAC algorithm). The architecture can be implemented, for example, as a system-on-chip (SOC) for a video/audio decoder for use high definition television broadcasting (HDTV) applications. Other such video/audio decoder applications are enabled as well.
Rendering Dynamic Objects Using Geometry Level-Of-Detail In A Graphics Processing Unit
Liang Peng - San Jose CA, US Wei-Wen Feng - Urbana IL, US
Assignee:
RAMBUS INC. - Los Altos CA
International Classification:
G06T 17/00
US Classification:
345420
Abstract:
The present embodiments provide a system for graphically rendering an object. This system operates first by pre-processing a geometry mesh for the object offline, wherein the geometry mesh is partitioned into a set of patches, and wherein each patch is bounded by a bounding box. The system then builds a multi-resolution representation for each of the set of patches. Next, during real time rendering, the system deforms the bounding boxes associated with the set of patches through superposition of object motions in each frame weighted by a set of predetermined mesh-skinning parameters. For each deformed bounding box, the system computes a geometry level-of-detail (LOD) value based on a projected area of the deformed bounding box in screen space. The system next deforms the object through a set of mesh skinning operations. The system then renders the deformed object based on the computed geometry LOD values for the set of patches and the multi-resolution representation for the geometry mesh.
Counterfeit Prevention Strategy For Pluggable Modules
Norman Tang - Los Altos CA, US Adam Jonathan Carter - San Jose CA, US David C. Lai - Mountain View CA, US Liang Ping Peng - Santa Clara CA, US Guoying Ding - Sunnyvale CA, US
Assignee:
CISCO TECHNOLOGY, INC. - San Jose CA
International Classification:
G06F 21/24 G06Q 30/00 G06Q 50/00 H04L 9/32
US Classification:
713168, 705 26, 726 22
Abstract:
A method is provided, including (a) upon a standard small form-factor pluggable (SFP) module being inserted into an SFP jack on a network host device, determining if the SFP module is a legacy device or a smart device, (b) upon determining that the SFP module is a legacy device, receiving a magic code from the SFP module and determining if the magic code is a valid magic code, and (c) upon determining that the SFP module is a smart device, performing a smart authentication process with the SFP module. Associated apparatuses and additional methods are also provided.
tackling challenges as diverse as predicting earthquakes and reducing energy consumption in mechanical devices," says Ph.D. researcher Liang Peng, who conducted the research project. This is no small matter: Friction is estimated to be responsible for more than 20% of our global energy consumption.