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Liang Ping Peng

age ~60

from Santa Clara, CA

Also known as:
  • Liang Ai Peng
  • Liang T Peng
  • Liang P Peng
  • Ping Peng
  • Liang-Ping Peng
  • Liangping Ping Peng
  • Liang-Ting Peng
  • Ping Peng Liangping
Phone and address:
4183 Tobin Cir, Santa Clara, CA 95054
(408)4929118

Liang Peng Phones & Addresses

  • 4183 Tobin Cir, Santa Clara, CA 95054 • (408)4929118
  • Sunnyvale, CA
  • 31 Wedgewood Cir, Eatontown, NJ 07724 • (732)5440814
  • 72 Wedgewood Cir, Eatontown, NJ 07724 • (732)5440814
  • 3520 Gilman Cmn, Fremont, CA 94538 • (510)6578218
  • Lake Grove, NY
  • Stony Brook, NY
  • Alameda, CA
  • 611 Santa Catalina Ter, Sunnyvale, CA 94085 • (408)3687262

Work

  • Position:
    Food Preparation and Serving Related Occupations

Education

  • Degree:
    Bachelor's degree or higher

Emails

Resumes

Liang Peng Photo 1

Senior Research Engineer

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Location:
Santa Clara, CA
Industry:
Computer Software
Work:
Oath
Senior Research Engineer

Yahoo
Research Engineer

Utah State University
Graduate Teaching Assistant

Yahoo May 2015 - Jul 2015
Summer Intern

Canon Usa May 2014 - Dec 2014
Senior Research Intern
Education:
Utah State University 2011 - 2015
Doctorates, Doctor of Philosophy, Computer Science
Kansas State University 2011
Master of Science, Masters
Kansas State University 2008 - 2011
Masters, Statistics
Emporia State University 2005 - 2008
Bachelors, Bachelor of Science, Economics
Skills:
Machine Learning
Data Mining
R
Java
Statistics
Python
Computer Science
Matlab
Image Processing
Sql
Data Analysis
Computer Vision
Artificial Intelligence
Deep Learning
Latex
Teaching
Software Engineering
Sas
C#
Research
Mathematics
.Net
Perl
C++ Language
Regression
Planning
Bayesian Networks
Face Recognition
Object Detection
Classification
Json
Economics
Gui
Object Tracking
Regression Analysis
Amazon Web Services
Batch Programming
Applied Mathematics
Databases
Interests:
Sns
Entrepreneurship
Technology
Startup
Machine Learning
Regression
Data Mining
Software Engineering
Liang Peng Photo 2

Thomas P Bowles Chair Professor Of Actuarial Science

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Location:
1063 Oaktree Dr, San Jose, CA 95129
Industry:
Telecommunications
Work:
Futurewei Technologies
Head of Ic Lab

Department of Risk Management and Insurance Gsu
Thomas P Bowles Chair Professor of Actuarial Science

Huawei Technologies
Senior Director, Technical Planning and Strategy, Ic Lab

Intel Corporation Oct 2008 - Jun 2014
Platform Architect

Chinese American Semiconductor Professional Association Oct 2008 - Jun 2014
Advisor , Chairman and President Board Director
Education:
Cornell University 1991 - 1998
Doctorates, Doctor of Philosophy, Computer Graphics
Peking University 1987 - 1991
Bachelors, Bachelor of Science, Astrophysics
Erasmus University Rotterdam
Skills:
Semiconductors
Asic
Soc
Ic
Computer Architecture
Embedded Systems
Simulations
Algorithms
Circuit Design
Product Management
System Architecture
Fpga
Leadership
Serdes
Perl
Eda
Debugging
Processors
Cross Functional Team Leadership
High Performance Computing
Embedded Software
Operational Execution
Mixed Signal
Team Leadership
Strategic Leadership
Hardware Architecture
3D Computer Graphics Algorithm
Engineering Management
R&D
Software Engineering
Technical Leadership
Image Processing
Signal Processing
Distributed Systems
Visionary Thinking
C/C++/Systemc
Interests:
Christianity
Kids
Investing
Sweepstakes
Nascar
Electronics
Home Improvement
Sports
Golf
Family Values
Collecting
Home Decoration
Languages:
Mandarin
Liang Peng Photo 3

Liang Peng

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Liang Peng Photo 4

Liang Peng

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Liang Peng Photo 5

Liang Peng

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Liang Peng Photo 6

Liang Peng

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Location:
United States
Name / Title
Company / Classification
Phones & Addresses
Liang Peng
President
CHINESE AMERICAN SEMICONDUCTOR PROFESSIONAL ASSOCIATION
Professional Organization
1159 Sonora Ct STE 105, Sunnyvale, CA 94086

Us Patents

  • System, Method And Article Of Manufacture For Shadow Mapping

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  • US Patent:
    6593923, Jul 15, 2003
  • Filed:
    Aug 16, 2000
  • Appl. No.:
    09/640505
  • Inventors:
    Walter E. Donovan - Milpitas CA
    Liang Peng - Sunnyvale CA
  • Assignee:
    Nvidia Corporation - Santa Clara CA
  • International Classification:
    G06T 1500
  • US Classification:
    345422
  • Abstract:
    A system, method and article of manufacture are provided for shadow mapping while rendering a primitive in a graphics pipeline. Initially, an offset operation is performed in order to generate a depth value while rendering a primitive. Further, a value of a slope associated with an edge of the primitive is identified. Thereafter, the depth value is conditionally clamped based on the value of the slope.
  • System, Method And Article Of Manufacture For Shadow Mapping

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  • US Patent:
    6690372, Feb 10, 2004
  • Filed:
    Dec 5, 2000
  • Appl. No.:
    09/730639
  • Inventors:
    Walter E. Donovan - Milpitas CA
    Liang Peng - Sunnyvale CA
  • Assignee:
    NVIDIA Corporation - Santa Clara CA
  • International Classification:
    G06T 1500
  • US Classification:
    345426
  • Abstract:
    A system, method and article of manufacture are provided for shadow mapping while rendering a primitive in a graphics pipeline. Initially, an offset operation is performed in order to generate a depth value while rendering a primitive. Further, a value of a slope associated with an edge of the primitive is identified. Thereafter, the depth value is conditionally clamped based on the value of the slope.
  • System, Method And Article Of Manufacture For Shadow Mapping

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  • US Patent:
    7119806, Oct 10, 2006
  • Filed:
    Sep 30, 2003
  • Appl. No.:
    10/676788
  • Inventors:
    Walter E. Donovan - Milpitas CA, US
    Liang Peng - Sunnyvale CA, US
  • Assignee:
    Nvidia Corporation - Santa Clara CA
  • International Classification:
    G06T 15/00
  • US Classification:
    345426
  • Abstract:
    A system, method and article of manufacture are provided for shadow mapping while rendering a primitive in a graphics pipeline. Initially, an offset operation is performed in order to generate a depth value while rendering a primitive. Further, a value of a slope associated with an edge of the primitive is identified. Thereafter, the depth value is conditionally clamped based on the value of the slope.
  • Atomic-Operation Coalescing Technique In Multi-Chip Systems

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  • US Patent:
    8473681, Jun 25, 2013
  • Filed:
    Feb 2, 2010
  • Appl. No.:
    13/143993
  • Inventors:
    Qi Lin - Los Altos Hills CA, US
    Liang Peng - San Jose CA, US
    Craig E. Hampel - Los Altos CA, US
    Thomas J. Sheffler - San Francisco CA, US
    Steven C. Woo - Saratoga CA, US
    Bohuslav Rychlik - San Diego CA, US
  • Assignee:
    Rambus Inc. - Sunnyvale CA
  • International Classification:
    G06F 13/00
  • US Classification:
    711121, 711124, 711141, 711E12023, 712 32
  • Abstract:
    A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
  • Digital Signal Processing Structure For Decoding Multiple Video Standards

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  • US Patent:
    20060126726, Jun 15, 2006
  • Filed:
    May 25, 2005
  • Appl. No.:
    11/137971
  • Inventors:
    Teng Lin - San Jose CA, US
    Hongjun Yuan - San Jose CA, US
    Weimin Zeng - San Jose CA, US
    Liang Peng - San Jose CA, US
  • International Classification:
    H04N 11/04
    H04N 7/12
    H04N 11/02
    H04B 1/66
  • US Classification:
    375240030, 375240250, 375240230, 375240240, 375240200, 375240120
  • Abstract:
    In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.
  • Two Pass Architecture For H.264 Cabac Decoding Process

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  • US Patent:
    20060126744, Jun 15, 2006
  • Filed:
    Jul 13, 2005
  • Appl. No.:
    11/181204
  • Inventors:
    Liang Peng - San Jose CA, US
    Ankur Shah - Sunnyvale CA, US
  • International Classification:
    H04N 7/12
    H04N 11/04
    H04N 11/02
    H04B 1/66
  • US Classification:
    375240260, 375240250, 375240240
  • Abstract:
    An architecture capable of stream parsing of the H.264 Content Based Adaptive Binary Arithmetic Coding (CABAC) format is disclosed. The architecture employs a two pass dataflow approach to implement the functions of CABAC bit parsing and decoding processes (based on the H.264 CABAC algorithm). The architecture can be implemented, for example, as a system-on-chip (SOC) for a video/audio decoder for use high definition television broadcasting (HDTV) applications. Other such video/audio decoder applications are enabled as well.
  • Rendering Dynamic Objects Using Geometry Level-Of-Detail In A Graphics Processing Unit

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  • US Patent:
    20090195541, Aug 6, 2009
  • Filed:
    Jan 29, 2009
  • Appl. No.:
    12/362122
  • Inventors:
    Liang Peng - San Jose CA, US
    Wei-Wen Feng - Urbana IL, US
  • Assignee:
    RAMBUS INC. - Los Altos CA
  • International Classification:
    G06T 17/00
  • US Classification:
    345420
  • Abstract:
    The present embodiments provide a system for graphically rendering an object. This system operates first by pre-processing a geometry mesh for the object offline, wherein the geometry mesh is partitioned into a set of patches, and wherein each patch is bounded by a bounding box. The system then builds a multi-resolution representation for each of the set of patches. Next, during real time rendering, the system deforms the bounding boxes associated with the set of patches through superposition of object motions in each frame weighted by a set of predetermined mesh-skinning parameters. For each deformed bounding box, the system computes a geometry level-of-detail (LOD) value based on a projected area of the deformed bounding box in screen space. The system next deforms the object through a set of mesh skinning operations. The system then renders the deformed object based on the computed geometry LOD values for the set of patches and the multi-resolution representation for the geometry mesh.
  • Counterfeit Prevention Strategy For Pluggable Modules

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  • US Patent:
    20100325432, Dec 23, 2010
  • Filed:
    Jun 23, 2009
  • Appl. No.:
    12/489608
  • Inventors:
    Norman Tang - Los Altos CA, US
    Adam Jonathan Carter - San Jose CA, US
    David C. Lai - Mountain View CA, US
    Liang Ping Peng - Santa Clara CA, US
    Guoying Ding - Sunnyvale CA, US
  • Assignee:
    CISCO TECHNOLOGY, INC. - San Jose CA
  • International Classification:
    G06F 21/24
    G06Q 30/00
    G06Q 50/00
    H04L 9/32
  • US Classification:
    713168, 705 26, 726 22
  • Abstract:
    A method is provided, including (a) upon a standard small form-factor pluggable (SFP) module being inserted into an SFP jack on a network host device, determining if the SFP module is a legacy device or a smart device, (b) upon determining that the SFP module is a legacy device, receiving a magic code from the SFP module and determining if the magic code is a valid magic code, and (c) upon determining that the SFP module is a smart device, performing a smart authentication process with the SFP module. Associated apparatuses and additional methods are also provided.

News

Control Over Friction, From Small To Large Scales

Control over friction, from small to large scales

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  • tackling challenges as diverse as predicting earthquakes and reducing energy consumption in mechanical devices," says Ph.D. researcher Liang Peng, who conducted the research project. This is no small matter: Friction is estimated to be responsible for more than 20% of our global energy consumption.
  • Date: Dec 01, 2023
  • Category: Science
  • Source: Google

Classmates

Liang Peng Photo 7

Liang Peng

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Schools:
Ohio University Athens OH 1988-1992
Community:
Terrence Martin
Liang Peng Photo 8

Fu-Shin High School, Taipei

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Graduates:
liang Peng (1985-1989),
Hong Hsin Chen (1989-1993)

Youtube

Liang Jingkun vs Xiang Peng | MS | WTT Conten...

Download the new WTT app and follow us on social media for a full 360 ...

  • Duration:
    15m 42s

Some tips on Peng, a special gift for the Chi...

Taichi #Taiji #Fajin #Neijin #Peng Learn Taiji Online: This one is t...

  • Duration:
    11m 26s

Liang Jingkun vs Xiang Peng | Round 2 - 4th C...

tabletennis #pingpong #...

  • Duration:
    17m 20s

Peng is the Jin that is full of emptiness

When we train Peng Jin, don't try to expand your Jin to resist the opp...

  • Duration:
    4m 45s

Piao Liang Peng You

Provided to YouTube by Universal Music Group Piao Liang Peng You Chua...

  • Duration:
    1m 55s

Fire Breath ni Liang Peng

  • Category:
    Comedy
  • Uploaded:
    25 Mar, 2009
  • Duration:
    30s

Flickr

Myspace

Liang Peng Photo 17

Liang Peng

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Locality:
Manhattan, Kansas
Gender:
Male
Birthday:
1943
Liang Peng Photo 18

liang peng

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Locality:
, China
Gender:
Male
Birthday:
1950
Liang Peng Photo 19

liang peng

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Locality:
, China
Gender:
Male
Birthday:
1950
Liang Peng Photo 20

liang peng

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Locality:
, China
Gender:
Male
Birthday:
1950

Googleplus

Liang Peng Photo 21

Liang Peng

Lived:
San Jose, CA
Nanjing
Nanjing, Beijing, Ithaca, Sunnyvale, Mountain View, San Jose
Work:
Intel - Computer Platform Architect
S3, Nvidia, Micronas, Rambus
Education:
Peking University, Cornell University
Liang Peng Photo 22

Liang Peng

Liang Peng Photo 23

Liang Peng

Liang Peng Photo 24

Liang Peng

Liang Peng Photo 25

Liang Peng

Liang Peng Photo 26

Liang Peng

Liang Peng Photo 27

Liang Peng

Liang Peng Photo 28

Liang Peng

Facebook

Liang Peng Photo 29

Liang Peng

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Liang Peng Photo 30

Liang Suit Peng

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Liang Peng Photo 31

Liang Peng

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Liang Peng Photo 32

Liang Peng

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Liang Peng Photo 33

Wang Liang Peng

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Liang Peng Photo 34

Liang Peng Yu

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Liang Peng Photo 35

Liang Peng Tan

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Liang Peng Photo 36

Liang Peng

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