Manish M Pandey

US Patent:

7266790, Sep 4, 2007

Filed:

Sep 4, 2003

Appl. No.:

10/656801

Inventors:

Manish Pandey - San Jose CA, US
Yung-Te Lai - Cupertino CA, US
Bret Siarkowski - Marlborough MA, US
Chih-Chang Lin - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 1, 716 6, 716 18

Abstract:

Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

US Patent:

7620918, Nov 17, 2009

Filed:

Aug 29, 2007

Appl. No.:

11/847177

Inventors:

Manish Pandey - San Jose CA, US
Yung-Te Lai - Cupertino CA, US
Chih-Chang Lin - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 3

Abstract:

Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

US Patent:

7620919, Nov 17, 2009

Filed:

Aug 29, 2007

Appl. No.:

11/847187

Inventors:

Manish Pandey - San Jose CA, US
Yung-Te Lai - Cupertino CA, US
Chih-Chang Lin - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5

Abstract:

Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

US Patent:

7644380, Jan 5, 2010

Filed:

May 15, 2006

Appl. No.:

11/433960

Inventors:

Manish Pandey - Saratoga CA, US
Samuel L. Kerner - Dorchester MA, US
Chih-chang Lin - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4

Abstract:

Method for analyzing a circuit composed of MOS devices. The method can be used to direct MOS devices in static and dynamic circuits and involves identifying an undirected MOS device that connects nets. Functions of the nets that cause each net to be logic values are defined as a function of inputs to the circuit. The defined functions can include pulldown functions or both pullup and pulldown functions. A set of rules is used to determine the direction of a signal that flows through a device and applies defined functions. The rules for analyzing static devices may differ from the rules for analyzing dynamic devices. Devices that are determined to have uni-directional signal flow can be directed. Additionally, devices having bi-directional signal flow and uni-directional observability can be directed.

US Patent:

7669165, Feb 23, 2010

Filed:

Oct 25, 2006

Appl. No.:

11/586879

Inventors:

Manish Pandey - San Jose CA, US
Rajat Arora - Sunnyvale CA, US
Chih-Chang Lin - Saratoga CA, US
Huan-Chih Tsai - Saratoga CA, US
Bharat Chandramouli - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 3

Abstract:

Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

US Patent:

7694251, Apr 6, 2010

Filed:

Oct 30, 2006

Appl. No.:

11/590076

Inventors:

Bharat Chandramouli - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Manish Pandey - San Jose CA, US
Chih-Chang Lin - Saratoga CA, US
Madan M. Das - Sunnyvale CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 4

Abstract:

Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.

US Patent:

7739629, Jun 15, 2010

Filed:

Oct 30, 2006

Appl. No.:

11/590657

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2, 716 7, 703 14

Abstract:

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

US Patent:

7962886, Jun 14, 2011

Filed:

Dec 7, 2007

Appl. No.:

11/952798

Inventors:

Manish Pandey - San Jose CA, US
Marcelo Glusman - San Jose CA, US
Angela Krstic - San Diego CA, US
Yee-Wing Hsieh - Pleasanton CA, US
Andy Lin - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716136

Abstract:

A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.