Manish A Sharma

US Patent:

6385083, May 7, 2002

Filed:

Aug 1, 2001

Appl. No.:

09/920225

Inventors:

Manish Sharma - Sunnyvale CA
Manoj Bhattacharyya - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11C 1114

US Classification:

365171, 365173, 365 63

Abstract:

A Magnetic Random Access Memory (MRAM) device includes an array of cells; and a plurality of first conductors on a first side of the array. The first conductors extend in a first direction and are offset from at least some of the memory cells.

US Patent:

6404674, Jun 11, 2002

Filed:

Apr 2, 2001

Appl. No.:

09/825461

Inventors:

Thomas C. Anthony - Sunnyvale CA
Manish Sharma - Sunnyvale CA

Assignee:

Hewlett Packard Company Intellectual Property Administrator - Fort Collins CO

International Classification:

G11C 1115

US Classification:

365173, 365171

Abstract:

A magnetic memory cell having read-write conductor that is wholly clad with a high magnetic permeability soft magnetic material for a pinned-on-the-fly soft ferromagnetic reference layer is disclosed. The magnetic memory cell includes a ferromagnetic data layer, an intermediate layer formed on the ferromagnetic data layer, and a soft ferromagnetic reference layer having a non-pinned orientation of magnetization formed on the intermediate layer. The soft ferromagnetic reference layer includes a read-write conductor and a ferromagnetic cladding that completely surrounds the read-write conductor to form a cladded read-write conductor. During a read operation, a read current flowing through the read-write conductor generates a read magnetic field that does not saturate the ferromagnetic cladding. During a write operation, a write current flowing through the read-write conductor generates a write magnetic field that saturates the ferromagnetic cladding and extends to the ferromagnetic data layer.

US Patent:

6434048, Aug 13, 2002

Filed:

Jul 20, 2001

Appl. No.:

09/908901

Inventors:

Lung T. Tran - Saratoga CA
Manish Sharma - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11C 700

US Classification:

36518519, 36518518, 36518522, 36518907

Abstract:

A method and circuit write a memory cell. The method applies a pulse train to a write line connected to the memory cell. The number of pulses in the pulse train is not predetermined. The method compares a value on the input side of the cell to a reference value, wherein the input side of the memory cell provides an indication that a writing operation is complete. The method discontinues the pulse train on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. Preferably, the pulses are short in width and large in magnitude. The method may optionally count the number of pulses in the pulse train, and discontinue the pulse train on the write line and/or declare the cell as unusable if the number of pulses exceeds a predetermined maximum. The circuit comprises a pulse train generator and a comparator. The pulse train generator has an output and an enable input.

US Patent:

6434060, Aug 13, 2002

Filed:

Jul 31, 2001

Appl. No.:

09/917882

Inventors:

Lung T. Tran - Saratoga CA
Manish Sharma - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11C 700

US Classification:

36518907, 36518909

Abstract:

A method and circuit write a memory cell. The method applies a pulse to a write line connected to the memory cell. The duration of the pulse is not predetermined. The method compares a value on the input side of the cell to a reference value. The method discontinues the pulse on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. The circuit comprises a pulse generator and a comparator. The pulse generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the write line, whereby the pulse is disabled or enabled on the write line depending upon comparator output.

US Patent:

6470120, Oct 22, 2002

Filed:

Dec 13, 2000

Appl. No.:

09/736789

Inventors:

Evan D. H. Green - San Jose CA
Manish Sharma - Santa Clara CA

Assignee:

New Focus, Inc. - San Jose CA

International Classification:

G02B 626

US Classification:

385 52, 385 67, 385 74, 385 90, 385 88, 385 93, 359813, 359822

Abstract:

Apparatus and associated method for aligning optical components including lenses, filters, lasers, fiber optics, etc. The apparatus aligns a first optic element and a second optic element and includes a frame and a sleeve. The frame defines a frame bore along a longitudinal axis thereof. The sleeve defines an eccentric bore configured to contain the first optic element or the second optic element. The sleeve is rotatably coupled in the frame bore to align the first optic element with the second optic element in a plane intersected by the longitudinal axis.

US Patent:

6473337, Oct 29, 2002

Filed:

Oct 24, 2001

Appl. No.:

09/983404

Inventors:

Lung T. Tran - Saratoga CA
Manish Sharma - Sunnyvale CA
Thomas C. Anthony - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11C 1115

US Classification:

365173, 365158, 365171

Abstract:

A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction can have a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The change in resistance state of the magnetic tunnel junction changes the resistance of the selected memory cell, which is detectable during a read operation.

US Patent:

6483734, Nov 19, 2002

Filed:

Nov 26, 2001

Appl. No.:

09/992426

Inventors:

Manish Sharma - Sunnyvale CA
Lung T. Tran - Saratoga CA

Assignee:

Hewlett Packard Company - Palo Alto CA

International Classification:

G11C 1702

US Classification:

365 97, 365 96, 365100, 365 46

Abstract:

A memory device includes memory cells having a re-writeable element and a write-once element in series with the re-writeable element. The re-writeable element is programmable between a high resistance state and a low resistance state. The write-once element can be an anti-fuse element that is programmable from a high resistance state to a low resistance state, or a fuse element that is programmable from a low resistance state to a high resistance state. The two possible states for the re-writeable element and the two possible states for the write-once element allow the memory cells to store four different bits.

US Patent:

6504221, Jan 7, 2003

Filed:

Sep 25, 2001

Appl. No.:

09/963932

Inventors:

Lung T. Tran - Saratoga CA
Manish Sharma - Sunnyvale CA
Manoj K. Bhattacharyya - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11C 1115

US Classification:

257421, 257422, 365173

Abstract:

A magnetic memory device includes a data ferromagnetic layer having a magnetization that can be oriented in either of two directions, a reference layer, and a spacer layer between the data and reference layers. The reference layer includes a dielectric layer, first and second conductors separated by the dielectric layer, and a ferromagnetic cladding on the first and second conductors. The memory device may be read by temporarily setting the magnetization of the reference layer to a known orientation, and determining a resistance state of the device.