Mark A Gilmer

US Patent:

6373113, Apr 16, 2002

Filed:

May 6, 1998

Appl. No.:

09/073755

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257411, 257410, 257412, 257344, 257369

Abstract:

An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 -cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900Â C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500 to 650Â C.

US Patent:

6727569, Apr 27, 2004

Filed:

Apr 21, 1998

Appl. No.:

09/063081

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX
Robert Paiz - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257513, 257506, 257510, 257639, 257649

Abstract:

A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

US Patent:

6147004, Nov 14, 2000

Filed:

Jul 21, 1998

Appl. No.:

9/120056

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 2100

US Classification:

438706

Abstract:

The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.

US Patent:

62146904, Apr 10, 2001

Filed:

Dec 18, 1997

Appl. No.:

8/993415

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2176

US Classification:

438400

Abstract:

The present invention generally provides a semiconductor device and fabrication process in which gate electrode formation is integrated with the formation of isolation regions. Consistent with one embodiment of the invention, the semiconductor device is formed by forming at least two adjacent gate electrode stacks of the substrate. A layer of dielectric material is formed over regions of the substrate between the two adjacent gate electrode stacks and portions of the dielectric material layer are selectively removed to leave an isolation block of the dielectric material between the two adjacent gate electrode stacks. The gate electrode stacks may, for example, have a thickness ranging from about 2,500 to 6,000. ANG. In accordance with one aspect of the invention, active regions are formed in the substrate between the isolation block and at least one of the gate electrode stacks.

US Patent:

61724076, Jan 9, 2001

Filed:

Apr 16, 1998

Appl. No.:

9/061552

Inventors:

Mark I. Gardner - Cedar Park TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2972

US Classification:

257410

Abstract:

An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide. In an alternative embodiment, the gate dielectric may be formed sufficiently thick such that sidewall spacers are unnecessary to prevent silicide bridging between the gate conductor and the junction regions. In another alternative embodiment, the lightly doped drain implant areas may be formed self-aligned to the gate electrode prior to spacer formation.

US Patent:

61653144, Dec 26, 2000

Filed:

Jun 7, 2000

Appl. No.:

9/588910

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micron Devices, Inc. - Austin TX

International Classification:

H01L 2100

US Classification:

156345

Abstract:

The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.

US Patent:

61976474, Mar 6, 2001

Filed:

Nov 23, 1998

Appl. No.:

9/198195

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438301

Abstract:

A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O. sub. 2. The ambient temperature of the first oxidation chamber is preferably maintained at a temperature less than approximately 300. degree. C.

US Patent:

59638109, Oct 5, 1999

Filed:

Dec 18, 1997

Appl. No.:

8/993414

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX
Thomas E. Spikes - Round Rock TX

Assignee:

Advanced Micro Devices - Austin TX

International Classification:

H01L 21336

US Classification:

438287

Abstract:

A semiconductor device having a nitrogen enhanced high permittivity gate insulating layer and a process for manufacturing such a device is provided. Consistent with one embodiment, a high permittivity gate insulating layer is formed over a substrate using a nitrogen bearing gas. The gate insulating layer has a dielectric constant of at least 20. At least one gate electrode is formed over the high permittivity gate insulating layer. An optional nitride capping layer can be formed between the high permittivity gate insulating layer and the gate electrode. The nitrogen bearing gas may include one or more nitrogen bearing species, such as NO, NF. sub. 3 or N2, for example. The use of nitrogen in the formation of a high permittivity gate insulating layer can, for example, reduce oxidation of the high permittivity layer and increase the ability to control the characteristics of the gate insulating layer.