Mark Joseph Hickey

US Patent:

7065101, Jun 20, 2006

Filed:

Nov 15, 2001

Appl. No.:

10/003366

Inventors:

Frederick J. Ziegler - Rochester MN, US
Mark J. Hickey - Rochester MN, US
Jack C. Randolph - Rochester MN, US
Susan M. Cox - Rochester MN, US
Dale J. Thomforde - Pine Island MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 3/22
H04J 3/06

US Classification:

370467, 370503, 370535, 375354, 710 71

Abstract:

An apparatus for enabling transmission of parallel data from a first parallel bus to a second parallel bus via a serial data channel includes a first logic element that generates a synchronization character used in a serial data transmission protocol upon detection of a parallel synchronization packet. A serializer converts data from the first logic element into a serial data stream. A de-serializer converts the serial data stream into a plurality of parallel data packets. A second logic element detects the synchronization character and converts the synchronization character into a parallel synchronization packet.

US Patent:

7079528, Jul 18, 2006

Filed:

Dec 13, 2001

Appl. No.:

10/022020

Inventors:

Frederick J. Ziegler - Rochester MN, US
Mark J. Hickey - Rochester MN, US
Jack C. Randolph - Rochester MN, US
Susan M. Cox - Rochester MN, US
Dale J. Thomforde - Pine Island MN, US
Robert N. Newshutz - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/66

US Classification:

370352, 370365, 370366, 370535, 370539, 341100, 341101

Abstract:

In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

US Patent:

7187863, Mar 6, 2007

Filed:

Dec 13, 2001

Appl. No.:

10/021961

Inventors:

Susan Marie Cox - Rochester MN, US
Mark Joseph Hickey - Rochester MN, US
Jack Chris Randolph - Rochester MN, US
Dale John Thomforde - Pine Island MN, US
Frederick Jacob Ziegler - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 14/00

US Classification:

398 43, 370536, 385 24

Abstract:

In a first aspect, a stream of data is transmitted by dividing the stream of data into a first substream and a second substream, transmitting the first substream in a first data channel, and transmitting the second substream in a second data channel. Before transmitting the first and second substreams, a first marker signal is inserted in the first substream and/or a second marker signal is inserted in the second substream. A receiver circuit receives the substreams, detects at least one marker signal, and reassembles the data stream from the substreams based on at least one detected marker signal. Numerous other aspects are provided.

US Patent:

7260765, Aug 21, 2007

Filed:

Dec 17, 2004

Appl. No.:

11/016217

Inventors:

Mark J. Hickey - Rochester MN, US
Robert A. Shearer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714779, 714774

Abstract:

In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in which the data is presented on the bus; and (3) performing the CRC on the data. Numerous other aspects are provided.

US Patent:

7385925, Jun 10, 2008

Filed:

Nov 4, 2004

Appl. No.:

10/981063

Inventors:

Bruce L. Beukema - Hayfield MN, US
Mark J. Hickey - Rochester MN, US
Robert A. Shearer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/26

US Classification:

370235, 370252

Abstract:

Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets.

US Patent:

7814299, Oct 12, 2010

Filed:

Nov 20, 2008

Appl. No.:

12/274560

Inventors:

Mark Joseph Hickey - Rochester MN, US
Adam James Muff - Rochester MN, US
Matthew Ray Tubbs - Rochester MN, US
Charles David Wait - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712208, 712210

Abstract:

A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.

US Patent:

7873816, Jan 18, 2011

Filed:

Nov 20, 2008

Appl. No.:

12/274420

Inventors:

Mark J Hickey - Rochester MN, US
Stephen J Schwinn - Woodbury MN, US
Matthew R Tubbs - Rochester MN, US
Charles D Wait - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

712228, 718108

Abstract:

A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching operations such as context save and/or load operations in advance of context switches performed in one or more of such paired hardware threads. By doing so, the overall latency of a context switch, where both the context for a process being switched from must be saved, and the context for the process being switched to must be loaded, may be reduced.

US Patent:

7948894, May 24, 2011

Filed:

Apr 30, 2008

Appl. No.:

12/113102

Inventors:

Bruce L. Beukema - Hayfield MN, US
Mark J. Hickey - Rochester MN, US
Robert A. Shearer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/26

US Classification:

370235, 370252

Abstract:

Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets.