Michael J Abraham

US Patent:

7366017, Apr 29, 2008

Filed:

Aug 22, 2006

Appl. No.:

11/507596

Inventors:

Michael M. Abraham - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/34

US Classification:

36518512, 36518517

Abstract:

A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block.

US Patent:

7961488, Jun 14, 2011

Filed:

Mar 3, 2008

Appl. No.:

12/073265

Inventors:

Michael M. Abraham - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/42

US Classification:

365 12, 36518503

Abstract:

A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a multi-level cell device. The method includes the steps of initializing the bit in the lower page and the bit in the upper page by storing a value of one in each of the bits. One or more bits in the lower page are then programmed such that a one is stored in the one or more bits of the lower page. One or more bits in the upper page are then programmed such that a one is stored in the one or more bits of the upper page. The one or more bits in the upper page are then reprogrammed such that the value in the one or more bits of the upper page transitions from a one to a zero. The transition from a one to a zero in the one or more bits of the upper page is used to mark for performance of a block management function the block.

US Patent:

8179706, May 15, 2012

Filed:

May 19, 2011

Appl. No.:

13/111247

Inventors:

Michael M. Abraham - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 11/42

US Classification:

365 12, 36518503

Abstract:

A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.

US Patent:

8498138, Jul 30, 2013

Filed:

Apr 24, 2012

Appl. No.:

13/454636

Inventors:

Michael M. Abraham - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G02B 6/00

US Classification:

365 12, 36518503

Abstract:

A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.

US Patent:

20120109896, May 3, 2012

Filed:

Mar 11, 2011

Appl. No.:

13/046420

Inventors:

Michael M. Abraham - Meridian ID, US
Peter Feeley - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G06F 17/30

US Classification:

707659, 707E17007

Abstract:

Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.

US Patent:

20130311715, Nov 21, 2013

Filed:

Jul 24, 2013

Appl. No.:

13/949822

Inventors:

Michael M. Abraham - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G06F 12/02

US Classification:

711103

Abstract:

A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.