Michael T Ho

US Patent:

7936199, May 3, 2011

Filed:

Feb 6, 2008

Appl. No.:

12/027124

Inventors:

Michael V. Ho - Allen TX, US
Tyler J. Gomm - Boise ID, US
Scott E. Smith - Plano TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1/04
H03K 3/00

US Classification:

327298, 327165, 327166, 327261, 327294

Abstract:

A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.

US Patent:

8169759, May 1, 2012

Filed:

Jan 28, 2008

Appl. No.:

12/020967

Inventors:

Michael V. Ho - Allen TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H02H 3/20

US Classification:

361 56, 361 911, 361111

Abstract:

Apparatus, systems, and methods are disclosed that operate to boost an electrical potential of a control terminal of a transistor from a signal on an input terminal of the transistor to render a channel in the transistor more conductive. Additional apparatus, systems, and methods are disclosed.

US Patent:

8508278, Aug 13, 2013

Filed:

May 2, 2011

Appl. No.:

13/099153

Inventors:

Michael V. Ho - Allen TX, US
Tyler J. Gomm - Boise ID, US
Scott E. Smith - Plano TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1/04
H03K 3/00

US Classification:

327298, 327291, 327293, 327299

Abstract:

A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.

US Patent:

20120215943, Aug 23, 2012

Filed:

Apr 27, 2012

Appl. No.:

13/458815

Inventors:

Michael V. Ho - Allen TX, US

International Classification:

G06F 3/00
H02H 9/04
G11C 7/10
G05F 3/02

US Classification:

710 5, 327535, 361 56, 327537, 36518905

Abstract:

Apparatus, systems, and methods are disclosed that operate to boost an electrical potential of a control terminal of a transistor from a signal on an input terminal of the transistor to render a channel in the transistor more conductive. Additional apparatus, systems, and methods are disclosed.

US Patent:

20210287731, Sep 16, 2021

Filed:

Mar 12, 2020

Appl. No.:

16/817095

Inventors:

- Boise ID, US
Michael V. Ho - Allen TX, US

International Classification:

G11C 11/4076
G11C 11/4096
G11C 11/4093
G11C 7/10
H03L 7/081

Abstract:

An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.

US Patent:

20200035290, Jan 30, 2020

Filed:

Oct 4, 2019

Appl. No.:

16/593675

Inventors:

- Boise ID, US
Michael V. Ho - Allen TX, US

International Classification:

G11C 11/4076
G11C 7/22
G11C 11/4093
G06F 13/16

Abstract:

A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.

US Patent:

20190347219, Nov 14, 2019

Filed:

May 9, 2018

Appl. No.:

15/975556

Inventors:

- Boise ID, US
Michael V. Ho - Allen TX, US

International Classification:

G06F 13/16
G06F 13/40
G11C 7/10
G11C 7/12

Abstract:

Memory devices having a reduced global data patch footprint and associated systems and methods. In some embodiments, a memory device is provided, comprising (a) a memory array including first and second sets of memory banks, (b) lower data terminals, (c) upper data terminals, and (d) an input/output (I/O) circuit including an internal data bus. The internal data bus can include a first plurality of global data lines in communication the first set of memory banks, a second plurality of global data lines in communication with the second set of memory banks, a third plurality of global data lines in communication with the first and second pluralities of global data lines, and a fourth plurality of global data lines in communication with the first and second pluralities of global data lines. The third plurality of global data lines is configured to bidirectionally transfer data to and from the lower terminals, and the fourth plurality of global data lines is configured to bidirectionally transfer data to and from the upper terminals.

US Patent:

20190259440, Aug 22, 2019

Filed:

Mar 19, 2018

Appl. No.:

15/924757

Inventors:

- Boise ID, US
Michael V. Ho - Allen TX, US

International Classification:

G11C 11/4076
G11C 7/22
G06F 13/16

Abstract:

A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.