Michael D Lam

US Patent:

6836081, Dec 28, 2004

Filed:

Oct 31, 2001

Appl. No.:

09/999157

Inventors:

David F. Swanson - Howell MI
James W. Stewart - San Jose CA
Michael K. Lam - San Jose CA
Marcello Criscione - Ragusa, IT

Assignee:

STMicroelectronics, Inc. - Carrollton TX
STMicroelectronics Srl
LumiLeds Lighting U.S., LLC - San Jose CA

International Classification:

H05B 3702

US Classification:

315307, 315224, 315308, 315309

Abstract:

An LED driver circuit and method are disclosed where a plurality of arrays of light emitting diodes each have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving the selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.

US Patent:

7086039, Aug 1, 2006

Filed:

Nov 13, 2002

Appl. No.:

10/293457

Inventors:

Michael Shungkai Lam - Milpitas CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/44

US Classification:

717136

Abstract:

A method of translating computer source code into optimized object code. The computer source code contains a first label statement defining a first label, a second label statement defining a second label, a third label statement defining a third label, and a computed goto statement for instructing a computer to branch to the first label or to the second label, but not to the third label. The method includes generating a list of labels contained within at least a portion of the computer source code. The list of labels includes the first label and the second label, but not the third label. The method also includes translating the computer source code into an intermediate language. The translation of the computer source code includes translating the computed goto statement into an indirect goto statement within the intermediate language. The method also includes generating object code that includes the first label and the second label but does not include the third label.

US Patent:

7418693, Aug 26, 2008

Filed:

Aug 18, 2005

Appl. No.:

11/207267

Inventors:

Frank E. Gennari - Berkeley CA, US
Ya-Chieh Lai - Antioch CA, US
Matthew W. Moskewicz - Berkeley CA, US
Michael C. Lam - Rancho Cucamonga CA, US
Gregory R. McIntyre - El Cerrito CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 12, 716 13, 716 14

Abstract:

Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image.

US Patent:

7653892, Jan 26, 2010

Filed:

Aug 18, 2005

Appl. No.:

11/207266

Inventors:

Frank E. Gennari - Berkeley CA, US
Ya-Chieh Lai - Antioch CA, US
Matthew W. Moskewicz - Berkeley CA, US
Michael C. Lam - Rancho Cucamonga CA, US
Gregory R. McIntyre - El Cerrito CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 20, 716 21

Abstract:

Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs. The standard design rule can be created from a 2D pattern of interest by defining an origin of a shape within the 2D pattern of interest, identifying features within the 2D pattern of interest, deriving parameters relative to the origin for each of the identified features, and writing the standard design rule script using the derived parameters.

US Patent:

7661087, Feb 9, 2010

Filed:

Dec 12, 2006

Appl. No.:

11/609903

Inventors:

Frank E. Gennari - Berkeley CA, US
Ya-Chieh Lai - Antioch CA, US
Matthew W. Moskewicz - Berkeley CA, US
Michael C. Lam - Rancho Cucamonga CA, US
Gregory R. McIntyre - El Cerrito CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 18, 716 19, 716 10

Abstract:

Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image.

US Patent:

7707542, Apr 27, 2010

Filed:

Dec 12, 2006

Appl. No.:

11/609904

Inventors:

Frank E. Gennari - Berkeley CA, US
Ya-Chieh Lai - Antioch CA, US
Matthew W. Moskewicz - Berkeley CA, US
Michael C. Lam - Rancho Cucamonga CA, US
Gregory R. McIntyre - El Cerrito CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G03F 9/00
G03F 1/00

US Classification:

716 21, 716 19, 430 5

Abstract:

Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image.

US Patent:

7752577, Jul 6, 2010

Filed:

Dec 12, 2006

Appl. No.:

11/609895

Inventors:

Frank E. Gennari - Berkeley CA, US
Ya-Chieh Lai - Antioch CA, US
Matthew W. Moskewicz - Berkeley CA, US
Michael C. Lam - Rancho Cucamonga CA, US
Gregory R. McIntyre - El Cerrito CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 19, 716 21

Abstract:

Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs. The standard design rule can be created from a 2D pattern of interest by defining an origin of a shape within the 2D pattern of interest, identifying features within the 2D pattern of interest, deriving parameters relative to the origin for each of the identified features, and writing the standard design rule script using the derived parameters.

US Patent:

7818707, Oct 19, 2010

Filed:

Dec 12, 2006

Appl. No.:

11/609901

Inventors:

Frank E. Gennari - Berkeley CA, US
Ya-Chieh Lai - Antioch CA, US
Matthew W. Moskewicz - Berkeley CA, US
Michael C. Lam - Rancho Cucamonga CA, US
Gregory R. McIntyre - El Cerrito CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 2, 716 11, 716 18

Abstract:

Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image.