Michael J Moon

US Patent:

7822897, Oct 26, 2010

Filed:

Jun 29, 2008

Appl. No.:

12/164083

Inventors:

Hirak Mitra - Sunnyvale CA, US
Raj Kulkarni - Sunnyvale CA, US
Richard Wicks - Sunnyvale CA, US
Michael Moon - Sunnyvale CA, US

International Classification:

G06F 13/00

US Classification:

710104, 710306

Abstract:

The present invention relates to a flexible and reconfigurable bus fabric for microelectronic processing units, which can offer efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the present reconfigurable bus fabric comprises a multistate intersection between two data buses. Preferably, the multistate intersection comprises at least two states, a connecting state connecting the two data buses, and a disconnecting state disconnecting the two data buses. The multistate intersection provides a reconfigurable bus fabric, allowing different connection configuration for the data buses. This reconfigurable bus fabric offers soft-configurability and soft-reconfigurability, using software programming to arrange the circuits' interconnections. Other configurations are also disclosed in exemplary embodiments.

US Patent:

7870366, Jan 11, 2011

Filed:

Jun 29, 2008

Appl. No.:

12/164080

Inventors:

Hirak Mitra - Sunnyvale CA, US
Raj Kulkarni - Sunnyvale CA, US
Richard Wicks - Sunnyvale CA, US
Michael Moon - Sunnyvale CA, US

International Classification:

G06F 15/167

US Classification:

712200, 712 19

Abstract:

The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.

US Patent:

8103855, Jan 24, 2012

Filed:

Jun 29, 2008

Appl. No.:

12/164086

Inventors:

Hirak Mitra - Sunnyvale CA, US
Raj Kulkarni - Sunnyvale CA, US
Richard Wicks - Sunnyvale CA, US
Michael Moon - Sunnyvale CA, US

Assignee:

Navosha Corporation - Sunnyvale CA

International Classification:

G06F 15/16

US Classification:

712 28, 712 16, 712 19, 712200

Abstract:

The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the present method chains a plurality of functional blocks together by software so that one functional block starts after the completion of another functional block. The configuration of the chain can be series, parallel, and any combination thereof, arranged to meet the circuit's objective. The chaining can be configured and re-configured, preferably by software input. The chaining can also be performed at design time or at run time. The chaining can also be modified, preferably at design time, but can also be modified at run time.

US Patent:

8156313, Apr 10, 2012

Filed:

Jun 29, 2008

Appl. No.:

12/164089

Inventors:

Hirak Mitra - Sunnyvale CA, US
Raj Kulkarni - Sunnyvale CA, US
Richard Wicks - Sunnyvale CA, US
Michael Moon - Sunnyvale CA, US

Assignee:

Navosha Corporation - Sunnyvale CA

International Classification:

G06F 15/16

US Classification:

712 28, 712 E9071

Abstract:

In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next functional component. Thus when the first functional component completes its processing, its output is ready to be accessed as input to the next functional component. In an embodiment, the memory device further comprises a partition mechanism for simultaneously accepting output writing from the first functional component and accepting input reading from the second functional component. In another embodiment, the present integrated circuit comprises at least two functional components and at least two memory devices, together with a controller for switching the connections between the functional components and the memory devices. The controller can comprise a multiplexer or a switching matrix.

US Patent:

20100287244, Nov 11, 2010

Filed:

May 11, 2009

Appl. No.:

12/464050

Inventors:

Richard Wicks - Sunnyvale CA, US
Hirak Mitra - Sunnyvale CA, US
Michael Moon - Sunnyvale CA, US

Assignee:

NAVOSHA CORPORATION - Sunnyvale CA

International Classification:

G06F 15/16

US Classification:

709206

Abstract:

Methods and apparatuses for establishing a trusted group of users to prevent undesirable communication by employing authenticated contact information. In an embodiment, the present invention embeds authenticated contact information to data communication composed by members of the trusted group. Authenticated contact information is preferably disposable contact information, changeable as desired, at a regular interval, or one-time contact information. In another embodiment, the present invention discloses a process of expanding an existing trusted group of users to an outsider, comprising embedding authenticated contact information of a member within the trusted group to a data communication composed by the outsider to a member of the trusted group.