Myung Jin Kong

US Patent:

7546557, Jun 9, 2009

Filed:

Sep 7, 2006

Appl. No.:

11/516996

Inventors:

Myung Jin Kong - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 17/50
H01L 27/148
H01L 23/58

US Classification:

716 1, 716 2, 716 5, 716 10, 257245, 257492, 257493

Abstract:

The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%-30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.

US Patent:

7137089, Nov 14, 2006

Filed:

Sep 1, 2004

Appl. No.:

10/932220

Inventors:

Myung Jin Kong - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 10, 716 11

Abstract:

The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%–30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.