Paul D Solomon

US Patent:

7627840, Dec 1, 2009

Filed:

Jul 13, 2006

Appl. No.:

11/457174

Inventors:

A J Kleinosowski - Austin TX, US
Philip J. Oldiges - Lagrangeville NY, US
Paul M. Solomon - Yorktown Heights NY, US
Richard Q. Williams - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
H01L 29/94

US Classification:

716 4, 716 5, 257297

Abstract:

A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e. g. , an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.