Paul J Solomon

US Patent:

6339002, Jan 15, 2002

Filed:

Feb 10, 2000

Appl. No.:

09/501226

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438283, 438299

Abstract:

A method of forming a double gate metal-oxide-semiconductor field effect transistor (MOSFET). The method includes planarizing a backgate mesa stack of a backgate using chemical mechanical polishing (CMP) to isolate the backgate mesa. A topgate mesa stack is formed and patterned. The backgate is trimmed using the topgate as a mask to transfer a topgate pattern to the backgate. Then, the trimmed backgate is isolated. In one particular embodiment, CMP is used to isolate and planarize the trimmed backgate.

US Patent:

6437422, Aug 20, 2002

Filed:

May 9, 2001

Appl. No.:

09/852078

Inventors:

Paul M. Solomon - Yorktown Heights NY
Jane Margaret Shaw - Branford CT
Cherie R. Kagan - Ossining NY
Christos Dimitrios Dimitrakopoulos - West Harrison NY
Tak Hung Ning - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2906

US Classification:

257618, 257 40

Abstract:

Active devices that have either a thread or a ribbon geometry. The thread geometry includes single thread active devices and multiple thread devices. Single thread devices have a central core that may contain different materials depending upon whether the active device is responsive to electrical, light, mechanical, heat, or chemical energy. Single thread active devices include FETs, electro-optical devices, stress transducers, and the like. The active devices include a semiconductor body that for the single thread devices is a layer about the core of the thread. For the multiple thread devices, the semiconductor body is either a layer on one or more of the threads or an elongated body disposed between two of the threads. For example, a FET is formed of three threads, one of which carries a gate insulator layer and a semiconductor layer and the other two of which are electrically conductive and serve as the source and drain. The substrates or threads are preferably flexible and can be formed in a fabric.

US Patent:

6444578, Sep 3, 2002

Filed:

Feb 21, 2001

Appl. No.:

09/791024

Inventors:

Cyril Cabral, Jr. - Ossining NY
Roy Arthur Carruthers - Stormville NY
Kevin K. Chan - Staten Island NY
Guy M. Cohen - Mohegan Lake NY
Kathryn Wilder Guarini - Yorktown Heights NY
James M. Harper - Yorktown Heights NY
Christian Lavoie - Ossining NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438682, 438655, 438597, 438630

Abstract:

The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a MâSi or MâSiâGe alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

US Patent:

6555880, Apr 29, 2003

Filed:

Jun 7, 2001

Appl. No.:

09/875187

Inventors:

Cyril Cabral, Jr. - Ossining NY
Kevin Kok Chan - Staten Island NY
Guy Moshe Cohen - Mohegan Lake NY
Kathryn Wilder Guarini - Yorktown Heights NY
Christian Lavoie - Ossining NY
Ronnen Andrew Roy - Ossining NY
Paul Michael Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31119

US Classification:

257384, 257382, 257754

Abstract:

A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.

US Patent:

6579614, Jun 17, 2003

Filed:

Mar 23, 2001

Appl. No.:

09/814766

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Fenton R. McFeely - Ossining NY
Paul M. Solomon - Yorktown Heights NY
John J. Yurkas - Stamford CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 900

US Classification:

428336, 428446, 428472, 428698, 428701

Abstract:

A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substrate, placing the structure into a vessel having a base pressure below approximately 10 torr, exposing the structure to a silane gas at a sufficiently high predetermined temperature and predetermined pressure to cause formation of a metal silicide layer on the refractory metal film, and exposing the structure to a second gas at a sufficiently high temperature and pressure to nitride the metal silicide layer into a nitrided layer.

US Patent:

6580132, Jun 17, 2003

Filed:

Apr 10, 2002

Appl. No.:

10/119799

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257365, 257347, 438233, 438164

Abstract:

A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

US Patent:

6603181, Aug 5, 2003

Filed:

Jan 16, 2001

Appl. No.:

09/760621

Inventors:

Paul M. Solomon - Yorktown Heights NY
Douglas A. Buchanan - Cortland Manor NY
Eduard A. Cartier - New York NY
Kathryn W. Guarini - Yorktown Heights NY
Fenton R. McFeely - New York NY
Huiling Shang - Bethlehem PA
John J. Yourkas - Stamford CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257412, 438910

Abstract:

A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.

US Patent:

6645861, Nov 11, 2003

Filed:

Apr 18, 2001

Appl. No.:

09/836197

Inventors:

Cyril Cabral, Jr. - Ossining NY
Kevin K. Chan - Staten Island NY
Guy Moshe Cohen - Mohegan Lake NY
Kathryn Wilder Guarini - Yorktown Heights NY
Christian Lavoie - Ossining NY
Paul Michael Solomon - Yorktown Heights NY
Ying Zhang - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438682, 438595, 438596, 438655, 438656, 438664, 438683

Abstract:

A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si , and selectively etching the unreacted silicon layer.