Paul G Solomon

US Patent:

6339002, Jan 15, 2002

Filed:

Feb 10, 2000

Appl. No.:

09/501226

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438283, 438299

Abstract:

A method of forming a double gate metal-oxide-semiconductor field effect transistor (MOSFET). The method includes planarizing a backgate mesa stack of a backgate using chemical mechanical polishing (CMP) to isolate the backgate mesa. A topgate mesa stack is formed and patterned. The backgate is trimmed using the topgate as a mask to transfer a topgate pattern to the backgate. Then, the trimmed backgate is isolated. In one particular embodiment, CMP is used to isolate and planarize the trimmed backgate.

US Patent:

6579614, Jun 17, 2003

Filed:

Mar 23, 2001

Appl. No.:

09/814766

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Fenton R. McFeely - Ossining NY
Paul M. Solomon - Yorktown Heights NY
John J. Yurkas - Stamford CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 900

US Classification:

428336, 428446, 428472, 428698, 428701

Abstract:

A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substrate, placing the structure into a vessel having a base pressure below approximately 10 torr, exposing the structure to a silane gas at a sufficiently high predetermined temperature and predetermined pressure to cause formation of a metal silicide layer on the refractory metal film, and exposing the structure to a second gas at a sufficiently high temperature and pressure to nitride the metal silicide layer into a nitrided layer.

US Patent:

6580132, Jun 17, 2003

Filed:

Apr 10, 2002

Appl. No.:

10/119799

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257365, 257347, 438233, 438164

Abstract:

A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

US Patent:

6762101, Jul 13, 2004

Filed:

Apr 11, 2003

Appl. No.:

10/411727

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438283, 438157, 438199, 438230, 438284, 438299

Abstract:

A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

US Patent:

6829919, Dec 14, 2004

Filed:

Nov 13, 2001

Appl. No.:

09/992544

Inventors:

Constantinos Sioutas - Los Angeles CA
Paul A. Solomon - Henderson NV

Assignee:

University of Southern California - Los Angeles CA

International Classification:

G01N 1500

US Classification:

73 2804, 73 2805

Abstract:

A system for monitoring an aerosol including a plurality of particles is provided. Each of the particles has a size. The system includes an impactor assembly to receive the aerosol at a first flow rate and remove an exhaust portion of the particles that are less than a minimum particle size or greater than a maximum particle size. A remaining portion of the particles is emitted at a second flow rate lower than the first flow rate. A first sensor measures a characteristic of the remaining portion of the particles.

US Patent:

6946696, Sep 20, 2005

Filed:

Dec 23, 2002

Appl. No.:

10/328285

Inventors:

Kevin K. Chan - Staten Island NY, US
Guy M. Cohen - Mohegan Lake NY, US
Meikei Ieong - Wappingers Falls NY, US
Ronnen A. Roy - Ossining NY, US
Paul Solomon - Yorktown Heights NY, US
Min Yang - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01C027/148

US Classification:

257250, 257365, 257288, 257412, 257388, 257347, 438157, 438283, 438279, 438299

Abstract:

A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

US Patent:

7078773, Jul 18, 2006

Filed:

Dec 23, 2002

Appl. No.:

10/328258

Inventors:

Kevin K. Chan - Staten Island NY, US
Hussein I. Hanafi - Basking Ridge NJ, US
Paul M. Solomon - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257365

Abstract:

A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.

US Patent:

7145212, Dec 5, 2006

Filed:

Jun 17, 2004

Appl. No.:

10/868791

Inventors:

Kevin K. Chan - Staten Island NY, US
Lijuan Huang - Mountain View CA, US
Fenton R. McFeely - Ossining NY, US
Paul M. Solomon - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257412, 257413, 257E21122, 438455

Abstract:

A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.