Paul Q Tsang

US Patent:

44425899, Apr 17, 1984

Filed:

Mar 5, 1981

Appl. No.:

6/240677

Inventors:

Ven Y. Doo - San Jose CA
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265
H01L 2128

US Classification:

29571

Abstract:

A transistor and method of forming the same are disclosed. A thick mesa of dielectric material is grown on a semiconductor substrate and two or more layers of polycrystalline silicon grown on the vertical sides of the mesa serve a masking function to define the gate region of the transistor with high accuracy. The mesa and the two or more polycrystalline layers remain in the final device.

US Patent:

43921493, Jul 5, 1983

Filed:

Jun 15, 1981

Appl. No.:

6/273705

Inventors:

Cheng T. Horng - San Jose CA
Robert O. Schwenker - San Jose CA
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2712

US Classification:

357 49

Abstract:

Disclosed is a self-aligned process for providing an improved bipolar transistor structure. The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0. 2 to 0. 3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

US Patent:

43098126, Jan 12, 1982

Filed:

Mar 3, 1980

Appl. No.:

6/126610

Inventors:

Cheng T. Horng - San Jose CA
Robert O. Schwenker - San Jose CA
Paul J. Tsang - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265
H01L 21285
H01L 2131

US Classification:

29578

Abstract:

Disclosed is a self-aligned process for providing an improved bipolar transistor structure. The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0. 2 to 0. 3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.