Phuc Dinh Do

US Patent:

6344684, Feb 5, 2002

Filed:

Jul 6, 2000

Appl. No.:

09/610865

Inventors:

Rafiqul Hussain - Fremont CA
Phuc Dinh Do - Santa Clara CA
Benjamin G. Tubera - Milpitas CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257697, 257690, 257692, 257693, 361760, 361764, 324755, 439 71, 439 74

Abstract:

A multi-layered pin grid array interposer used in a test socket for testing and converting a package having a non-pin grid array footprint to a pin grid array footprint. The multi-layered pin grid array interposer test socket includes a multi-layered pin grid array interposer, a semiconductor device mounted on a package having a non-grid array footprint and a fastener. The multi-layered pin grid array interposer includes a top signal layer having bonding pads on an upper surface, a bottom signal layer having a pin grid array footprint on a bottom surface, at least one power layer between ground layers, the ground layers being between the top signal layer and bottom signal layer, and a links for connecting the plurality of bonding pads to the pins of the pin grid array footprint. The fastener presses the package against the multi-layered pin grid array interposer connecting the leads of the package with the bonding pads.