Raymond Leonard Kallaher

US Patent:

20230005743, Jan 5, 2023

Filed:

Sep 1, 2022

Appl. No.:

17/901405

Inventors:

- Redmond WA, US
Sergei V. GRONIN - West Lafayette IN, US
Raymond L. KALLAHER - West Lafayette IN, US
Michael James MANFRA - West Lafayette IN, US

International Classification:

H01L 21/02
H01L 21/265
H01L 29/06

Abstract:

The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.

US Patent:

20210375623, Dec 2, 2021

Filed:

May 29, 2020

Appl. No.:

16/887480

Inventors:

- Redmond WA, US
Sergei V. GRONIN - West Lafayette IN, US
Raymond L. KALLAHER - West Lafayette IN, US
Michael James MANFRA - West Lafayette IN, US

International Classification:

H01L 21/02
H01L 21/321

Abstract:

The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 Å. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.

US Patent:

20210375624, Dec 2, 2021

Filed:

May 29, 2020

Appl. No.:

16/887635

Inventors:

- Redmond WA, US
Sergei V. GRONIN - West Lafayette IN, US
Raymond L. KALLAHER - West Lafayette IN, US
Michael James MANFRA - West Lafayette IN, US

International Classification:

H01L 21/02
H01L 29/06
H01L 21/265

Abstract:

The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.

US Patent:

20210376572, Dec 2, 2021

Filed:

May 27, 2020

Appl. No.:

16/884439

Inventors:

- Redmond WA, US
Geoffrey Charles GARDNER - West Lafayette IN, US
Raymond Leonard KALLAHER - West Lafayette IN, US

Assignee:

Microsoft Technology Licensing, LLC - Redmond WA

International Classification:

H01S 5/34
H01S 5/343
H01S 5/04
H01S 5/042

Abstract:

A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.

US Patent:

20210280417, Sep 9, 2021

Filed:

Mar 5, 2020

Appl. No.:

16/810266

Inventors:

- Redmond WA, US
Sergei V. GRONIN - West Lafayette IN, US
Raymond L. KALLAHER - West Lafayette IN, US

International Classification:

H01L 21/02

Abstract:

A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.

US Patent:

20210280763, Sep 9, 2021

Filed:

Dec 23, 2019

Appl. No.:

16/725710

Inventors:

- Redmond WA, US
Raymond L. KALLAHER - West Lafayette IN, US
Sergei V. GRONIN - West Lafayette IN, US
Michael James MANFRA - West Lafayette IN, US

International Classification:

H01L 39/22
H01L 39/02
H01L 39/08
H01L 39/24

Abstract:

A semiconductor-superconductor hybrid structure includes a semiconductor layer and a superconductor heterostructure on the semiconductor layer. The superconductor heterostructure includes a first superconductor layer on the semiconductor layer and a second superconductor layer on the first superconductor layer. The first superconductor layer comprises a first superconducting material and the second superconductor layer comprises a second superconducting material that is different from the first superconducting material. By providing the superconductor heterostructure as multiple layers of different superconducting materials, the superconducting and physical properties of the superconductor heterostructure can be improved compared to conventional superconducting homostructures, thereby increasing the performance of the semiconductor-superconductor hybrid structure.

US Patent:

20210265161, Aug 26, 2021

Filed:

Feb 25, 2020

Appl. No.:

16/800758

Inventors:

- Redmond WA, US
Raymond L. KALLAHER - West Lafayette IN, US
Sergei V. GRONIN - West Lafayette IN, US

International Classification:

H01L 21/02
B82Y 40/00
B82Y 30/00
H01L 27/18
H01L 29/06

Abstract:

A method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.

US Patent:

20210210599, Jul 8, 2021

Filed:

Jan 8, 2020

Appl. No.:

16/736930

Inventors:

- Redmond WA, US
Sergei V. GRONIN - West Lafayette IN, US
Raymond L. KALLAHER - West Lafayette IN, US
Michael James MANFRA - West Lafayette IN, US

International Classification:

H01L 29/06
H01L 29/20
H01L 21/02
H01L 21/3205

Abstract:

A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.