Raymond Phillip Scholer

US Patent:

6538264, Mar 25, 2003

Filed:

Aug 28, 2001

Appl. No.:

09/941089

Inventors:

Tim J. Corbett - Boise ID
Raymond P. Scholer - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2350

US Classification:

257 48, 257203, 257620, 257208, 257210, 257202, 257784, 257786

Abstract:

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

US Patent:

6770906, Aug 3, 2004

Filed:

Feb 19, 2003

Appl. No.:

10/368964

Inventors:

Tim J. Corbett - Boise ID
Raymond P. Scholer - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2350

US Classification:

257 48, 257203, 257620, 257208, 257210, 257207, 257784, 257211, 257212

Abstract:

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

US Patent:

59362600, Aug 10, 1999

Filed:

Aug 21, 1997

Appl. No.:

8/916114

Inventors:

Tim J. Corbett - Boise ID
Raymond P. Scholer - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2350
H01L 2704
H01L 2718
G01R 3102

US Classification:

257 48

Abstract:

A semiconductor test chip including a plurality test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

US Patent:

6157046, Dec 5, 2000

Filed:

Apr 23, 1999

Appl. No.:

9/298300

Inventors:

Tim J. Corbett - Boise ID
Raymond P. Scholer - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2350
H01L 2704
H01L 2718
G01R 3102

US Classification:

257 48

Abstract:

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

US Patent:

63202018, Nov 20, 2001

Filed:

Jul 20, 2000

Appl. No.:

9/619940

Inventors:

Tim J. Corbett - Boise ID
Raymond P. Scholer - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2350
H01L 2704
H01L 2718
G01R 3102

US Classification:

257 48

Abstract:

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

US Patent:

57510156, May 12, 1998

Filed:

Nov 17, 1995

Appl. No.:

8/560544

Inventors:

Tim J. Corbett - Boise ID
Raymond P. Scholer - Boise ID
Fernando Gonzalez - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2350
H01L 2704
H01L 2718
G01R 3102

US Classification:

257 48

Abstract:

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.