Thomas R Scholer

US Patent:

6433371, Aug 13, 2002

Filed:

Jan 29, 2000

Appl. No.:

09/493428

Inventors:

Thomas C. Scholer - San Jose CA
Allen S. Yu - Fremont CA
Paul J. Steffan - Elk Grove CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257288, 257331, 257336, 257412

Abstract:

Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

US Patent:

6448606, Sep 10, 2002

Filed:

Feb 24, 2000

Appl. No.:

09/513261

Inventors:

Allen S. Yu - Fremont CA
Thomas C. Scholer - San Jose CA
Paul J. Steffan - Elk Grove CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257315, 257317, 257510, 257515, 438296

Abstract:

A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.

US Patent:

6524916, Feb 25, 2003

Filed:

May 1, 2002

Appl. No.:

10/137568

Inventors:

Thomas C. Scholer - San Jose CA
Allen S. Yu - Fremont CA
Paul J. Steffan - Elk Grove CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438270, 438271, 438585, 438587, 438588, 438592

Abstract:

An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

US Patent:

59857536, Nov 16, 1999

Filed:

Aug 19, 1998

Appl. No.:

9/136866

Inventors:

Allen S. Yu - Fremont CA
Paul J. Steffan - Elk Grove CA
Thomas C. Scholer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438637

Abstract:

Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.

US Patent:

60252723, Feb 15, 2000

Filed:

Sep 28, 1998

Appl. No.:

9/161879

Inventors:

Allen S. Yu - Fremont CA
Thomas C. Scholer - San Jose CA
Paul J. Steffan - Elk Grove CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

438697

Abstract:

A method of manufacturing a semiconductor device including a step of filling crevices or non-level regions formed during the manufacture of the semiconductor device with a spin-on dielectric material. The spin-on dielectric material prevents conductive material from filling the crevices and causing the device to fail.

US Patent:

61331406, Oct 17, 2000

Filed:

Oct 2, 1998

Appl. No.:

9/165782

Inventors:

Allen S. Yu - Fremont CA
Paul J. Steffan - Elk Grove CA
Thomas C. Scholer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438624

Abstract:

A method of manufacturing a semiconductor device with dual damascene structures. A first and second layer of interlayer dielectric separated by a first layer of etch stop material is formed on the surface of a semiconductor substrate on and in which active devices have been formed. A second layer of an etch stop material is formed on the surface of the second layer of interlayer dielectric. A layer of photoresist is formed on the second layer of etch stop material and is patterned and etched to expose portions of the second etch stop material. The exposed portions of the second etch stop material are anisotropically etched exposing portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are first anisotropically etched and then isotropically etched. The etch stop layer between the first and second interlayer dielectric is anisotropically etched and the first layer of interlayer dielectric is anisotropically etched.

US Patent:

60252596, Feb 15, 2000

Filed:

Jul 2, 1998

Appl. No.:

9/109113

Inventors:

Allen S. Yu - Fremont CA
Paul J. Steffan - Elk Grove CA
Thomas Charles Scholer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438618

Abstract:

A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench.

US Patent:

61005932, Aug 8, 2000

Filed:

Feb 27, 1998

Appl. No.:

9/032362

Inventors:

Allen S. Yu - Fremont CA
Paul J. Steffan - Elk Grove CA
Thomas C. Scholer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348
H01L 2352
H01L 2940

US Classification:

257777

Abstract:

A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.