Richard Chien Shen Huang

US Patent:

6335273, Jan 1, 2002

Filed:

Nov 19, 1999

Appl. No.:

09/443376

Inventors:

Richard J. Huang - Cupertino CA
Guarionex Morales - Santa Clara CA
Simon Chan - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438622, 438624, 438683, 438685, 438687, 257758

Abstract:

A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

US Patent:

6346467, Feb 12, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649027

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Nagoya, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 213205

US Classification:

438594, 438264, 438595

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

US Patent:

6355546, Mar 12, 2002

Filed:

Aug 11, 1999

Appl. No.:

09/371922

Inventors:

Richard J. Huang - Cupertino CA
Lewis Shen - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438585, 438584, 438258, 438259, 257202

Abstract:

A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include thermally growing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by thermal oxidation at a temperature of about 800Â C. to about 900Â C. in an atmosphere comprising oxygen or steam. A silicon oxynitride or silicon-rich silicon nitride ARC is then formed on the thermally grown protective silicon oxide buffer layer and a photoresist layer is formed on the ARC. The photoresist layer is patterned to form a mask and the underlying silicon layer etched to form a conductive feature, e. g. , gate electrode. The photoresist mask is then removed and the ARC is stripped with hot phosphoric acid or by dry etching, while the thermally grown silicon oxide buffer layer protects the underlying silicon layer from damage.

US Patent:

6361837, Mar 26, 2002

Filed:

Jan 15, 1999

Appl. No.:

09/232359

Inventors:

Suzette K. Pangrle - Cupertino CA
Richard J. Huang - Cupertino CA
Shekhar Pramanick - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B05D 306

US Classification:

427552, 427533, 427504, 427503, 427526, 438781, 438788, 438792

Abstract:

The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

US Patent:

6387825, May 14, 2002

Filed:

Nov 12, 1998

Appl. No.:

09/191435

Inventors:

Lu You - Santa Clara CA
Dawn Hopper - San Jose CA
Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131

US Classification:

438782, 427240

Abstract:

This invention describes improved apparatus and methods for spin-on deposition of thin films applicable to the manufacture of semiconductor devices. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films.

US Patent:

6388309, May 14, 2002

Filed:

Oct 12, 2000

Appl. No.:

09/687180

Inventors:

Lu You - Santa Clara CA
Dawn M. Hopper - San Jose CA
Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2358

US Classification:

257632, 257634, 118723 E, 427255391, 427535

Abstract:

An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.

US Patent:

6400023, Jun 4, 2002

Filed:

Jan 22, 2001

Appl. No.:

09/765666

Inventors:

Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257758, 257783

Abstract:

An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric layer. A second interlayer dielectric layer containing fluorine is formed on the second etch stop layer by deposition. The first and second interlayer dielectric layers and the first and second etch stop layers are etched to form at least one trench and at least one via. The at least one trench and the at least one via are treated with an H /N plasma in-situ, wherein a fluorine-depleted region in the first and second interlayer dielectric layers is formed, and wherein a nitrided region is formed adjacent the fluorine-depleted region, with the nitrided region corresponding to a side surface of the at least one trench and the at least one via. A barrier metal layer is deposited in the at least one trench and the at least one via, whereby the nitrided region provides a passivation layer by which fluorine in the fluorine-depleted region is kept from leeching into the barrier metal layer. The at least one trench and the at least one via are then filled with either copper or aluminum.

US Patent:

6400030, Jun 4, 2002

Filed:

May 30, 2000

Appl. No.:

09/583817

Inventors:

Fei Wang - San Jose CA
Robin Cheung - Cupertino CA
Mark S. Chang - Los Altos CA
Richard J. Huang - Cupertino CA
Angela T. Hui - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257774, 438633

Abstract:

An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.