Richard T Huang

US Patent:

6346467, Feb 12, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649027

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Nagoya, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 213205

US Classification:

438594, 438264, 438595

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

US Patent:

6429108, Aug 6, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/652136

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Tokyo, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kawasaki

International Classification:

H01L 213205

US Classification:

438587

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.

US Patent:

6444593, Sep 3, 2002

Filed:

Aug 12, 1999

Appl. No.:

09/373483

Inventors:

Minh Van Ngo - Fremont CA
Richard J. Huang - Cupertino CA
Guarionex Morales - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21425

US Classification:

438788, 438513, 438624, 438680, 438758, 438761, 438774, 438775

Abstract:

A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.

US Patent:

6492258, Dec 10, 2002

Filed:

Jun 14, 2001

Appl. No.:

09/881831

Inventors:

Minh Van Ngo - Union City CA
Paul R. Besser - Sunnyvale CA
Matthew Buynoski - Palo Alto CA
John Caffall - San Carlos CA
Nick Maccrae - San Jose CA
Richard J. Huang - Cupertino CA
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438622, 438623, 438625, 438648, 438656, 438688, 257765, 257763, 257764

Abstract:

A method for making 0. 25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

US Patent:

6596631, Jul 22, 2003

Filed:

Jul 26, 2000

Appl. No.:

09/626455

Inventors:

Minh Van Ngo - Fremont CA
Hartmut Ruelke - Dresden Wilschdorf, DE
Lothar Mergili - Radebeul, DE
Joerg Hohage - Dresden, DE
Lu You - Santa Clara CA
Robert A. Huertas - Hollister CA
Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 244

US Classification:

438653, 438586, 438627, 438643, 438687, 438913

Abstract:

The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.

US Patent:

6635943, Oct 21, 2003

Filed:

Mar 22, 2000

Appl. No.:

09/533617

Inventors:

Angela T. Hui - Fremont CA
Tuan Duc Pham - Santa Clara CA
Richard J. Huang - Cupertino CA
Mark T. Ramsbey - Sunnyvale CA
Lu You - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257506, 257314, 257315, 257316, 257317, 257318, 257319, 257320, 257321, 257322, 257323, 257390

Abstract:

A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

US Patent:

6653202, Nov 25, 2003

Filed:

Jan 17, 2003

Appl. No.:

10/347064

Inventors:

Philip A. Fisher - Foster City CA
Richard J. Huang - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21762

US Classification:

438424, 438692

Abstract:

An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.

US Patent:

6869734, Mar 22, 2005

Filed:

Dec 30, 2002

Appl. No.:

10/331681

Inventors:

Christopher F. Lyons - Fremont CA, US
Cyrus E. Tabery - Sunnyvale CA, US
Richard J. Huang - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F009/00

US Classification:

430 5

Abstract:

An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of less than 70 nanometers.