Richard David Ross

Address:

PO Box 30732, Phoenix, AZ 85046

Phone:

(602)5747441

VIN:

5J6RE38709L006804

Make:

HONDA

Model:

CR-V

Year:

2009

US Patent:

6511866, Jan 28, 2003

Filed:

Jul 12, 2001

Appl. No.:

09/904583

Inventors:

Raymond S. Bregante - San Rafael CA
Tony Shaffer - Alameda CA
K. Scott Mellen - Central Square NY
Richard J. Ross - Moraga CA

Assignee:

RJR Polymers, Inc. - Oakland CA

International Classification:

H01L 2144

US Classification:

438127, 438106, 438118, 438121, 438456

Abstract:

Semiconductor circuit devices (dies) are incorporated into moisture-impenetrable electronic packages by forming enclosures around the die in three separate partsâbase, sidewalls, and lid. The die is first soldered or otherwise bonded to the base, followed by attachment of the sidewalls to the base, and finally the lid to the sidewalls. For procedures involving a heat-conductive base and a high soldering temperature, the die can be secured to the base at the high soldering temperature, followed by application of the sidewalls to the base at a significantly lower temperature, avoiding potential high-temperature damage to the sidewalls. Plastic sidewalls which would otherwise deteriorate or become distorted upon exposure to the high soldering temperature can thus be used. For electronic packages in general, the use of plastic sidewalls allows the use of combinations of materials for the lid and base that are otherwise incompatible, and reduces or eliminates the incidence of failure due to stress fractures that occur during the high temperatures encountered in fabrication, assembly, testing, or use of the package.

US Patent:

7089251, Aug 8, 2006

Filed:

Jun 26, 2000

Appl. No.:

09/602713

Inventors:

Richard A. Ross - Berkeley CA, US

Assignee:

Hewlett-Packard and Development Company, L.P. - Houston TX

International Classification:

G06F 17/30

US Classification:

707101, 707 10, 717153

Abstract:

Methods for processing condensed computer code are disclosed herein. The condensed computer code includes index references that take the place of code structures found in corresponding executable computer code. The condensed computer code, as well as one or more lists that map the index references found in the condensed computer code to the code structures found in the executable computer code, are transmitted to a user system. The condensed computer code is executed by fetching opcodes and operands from the computer code, and then executing the fetched opcodes. If a fetched operand is an index reference, the fetched operand is resolved by using the index reference as an index into one of the lists.

US Patent:

7305615, Dec 4, 2007

Filed:

Jul 3, 2002

Appl. No.:

10/189952

Inventors:

Richard Ross - Berkeley CA, US

Assignee:

Gigalogix, Inc. - Oakland CA

International Classification:

G06N 3/00

US Classification:

715513

Abstract:

According to the present invention, methods and apparatus are provided for improving the efficiency of data parsing. Data parsing can be applied to a variety of different types of data in various computer systems and appliances. Some of the methods and apparatus provided include techniques for scanning, verifying, calculating hash values, copying, and white space handling.

US Patent:

7430650, Sep 30, 2008

Filed:

Jun 13, 2005

Appl. No.:

11/151801

Inventors:

Richard A. Ross - Berkeley CA, US

International Classification:

G06F 12/00

US Classification:

711213, 711137, 712207

Abstract:

Cache prefetching algorithm uses previously requested address and data patterns to predict future data needs and prefetch such data from memory into cache. A requested address is compared to previously requested addresses and returned data to compute a set of increments, and the set of increments is added to the currently requested address and returned data to generate a set of prefetch candidates. Weight functions are used to prioritize prefetch candidates. The prefetching method requires no changes to application code or operation system (OS) and is transparent to the compiler and the processor. The prefetching method comprises a parallel algorithm well-suited to implementation on an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA), or to integration into a processor.

US Patent:

7962903, Jun 14, 2011

Filed:

Jun 5, 2007

Appl. No.:

11/758204

Inventors:

Richard A. Ross - Berkeley CA, US

International Classification:

G06F 9/45
G06F 3/00

US Classification:

717140, 715751, 715758

Abstract:

Systems and methods for processing message subscriptions using pre-compiled code-blocks for expression evaluation. In one embodiment, a system is configured find a set of unique clauses in a set of expressions representing message subscriptions, express the expressions as Boolean functions of the unique clauses, and compile the Boolean functions into a set of assembly instructions for efficient expression evaluation. In another embodiment, a system is configured to receive a message, generate a set of True/False assignments to a set of clauses in a set of expressions, and evaluate the expressions using an efficient compiled expression evaluation code-block.

US Patent:

8028228, Sep 27, 2011

Filed:

Oct 23, 2007

Appl. No.:

11/876994

Inventors:

Richard A. Ross - Berkeley CA, US

International Classification:

G06N 3/00

US Classification:

715234

Abstract:

According to the present invention, methods and apparatus are provided for improving the efficiency of data parsing. Data parsing can be applied to a variety of different types of data in various computer systems and appliances. Some of the methods and apparatus provided include techniques for scanning, verifying, calculating hash values, copying, and white space handling.

US Patent:

8336037, Dec 18, 2012

Filed:

May 16, 2007

Appl. No.:

11/749675

Inventors:

Richard A. Ross - Berkeley CA, US

International Classification:

G06F 9/45
G06F 9/44

US Classification:

717143, 717116, 717136, 717142

Abstract:

Client Native method Interface (CNI) minimizing eXtensible Mark-up Language (XML) parsing is provided using array pair data structures. An empty array pair is passed to an engine from client code via a CNI call. The engine parses the XML document and fills the array pair with fixed width elements. The filled array pair is passed back to client code. The client code iterates through the elements in the array pair and invokes the appropriate handlers or builds appropriate tree objects for Document Object Model parsing. Thus, one CNI call passes the empty array pair from client code to the engine, and the filled array pair is returned from the engine to client code. Individual sets of CNI calls for each element are avoided, minimizing the number of CNI calls. Further, since elements in the array pair are of fixed width, they can be processed more efficiently by the client code.

US Patent:

58161589, Oct 6, 1998

Filed:

Feb 2, 1998

Appl. No.:

8/952336

Inventors:

Richard J. Ross - Moraga CA

Assignee:

RJR Polymers, Inc. - Oakland CA

International Classification:

B41F 140

US Classification:

101324

Abstract:

Printing of a pattern from a die to a surface is performed by immersing the die in a bath of liquid print material with the die surface facing upward, then either lowering the bath liquid level or raising the die to expose the die surface wet with liquid print material, and contacting the surface to be printed with the wet die surface.