Robert G Solomon

US Patent:

6792506, Sep 14, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/113023

Inventors:

Robert Solomon - Kensington NH
Jeffrey Brown - Shrewsbury MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1316

US Classification:

711114, 711150, 710 22, 710 65

Abstract:

A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. User memory may pass through memory in a single hop by combining parity generation with FIFO buffering in the read and write user data paths. Independent memory channels may be controlled to level the load providing high memory bandwidth.

US Patent:

6877059, Apr 5, 2005

Filed:

Mar 29, 2002

Appl. No.:

10/109997

Inventors:

Robert Solomon - Kensington NH, US
Jeffrey Brown - Shrewsbury MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F013/14

US Classification:

710305, 710 22, 710 72, 711100

Abstract:

A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The preferred embodiment provides a store and forward architecture configured around a switch with prioritization on data pathways critical to high throughput.

US Patent:

7209979, Apr 24, 2007

Filed:

Mar 29, 2002

Appl. No.:

10/113027

Inventors:

Robert Solomon - Kensington NH, US
Jeffrey Brown - Shrewsbury MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/16

US Classification:

709249

Abstract:

A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The communications architecture provides saturation of user data pathways with low complexity and low latency by employing multiple memory channels under software control, an efficient parity calculation mechanism and other features.

US Patent:

8099554, Jan 17, 2012

Filed:

Dec 31, 2007

Appl. No.:

11/967940

Inventors:

Robert C. Solomon - Kensington NH, US
Kiran Madnani - Framingham MA, US
David W. DesRoches - Methuen MA, US
Roy E. Clark - Hopkinton MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/00
G06F 11/00

US Classification:

711118, 711102, 711104, 711105, 711113, 711114, 711119, 714 624

Abstract:

A system, method and computer program product for receiving on a non-volatile, solid-state, cache memory system, a data segment, including a plurality of data elements, from one or more of a volatile, solid-state, cache memory system and a non-volatile, electromechanical memory system. The data segment may be stored on the non-volatile, solid-state, cache memory system. Each data element includes one or more data extents.

US Patent:

20100163471, Jul 1, 2010

Filed:

Dec 30, 2008

Appl. No.:

12/345856

Inventors:

Irving Elyanow - Lexington MA, US
John Herbert - Marlborough MA, US
Robert Lee Solomon - Seattle WA, US
Nishith Vora - Bensalem PA, US
Lanny D. Weimer - Ellicott City MD, US

International Classification:

C02F 9/10
C02F 9/08
C02F 9/04
C02F 103/08

US Classification:

210176, 210260, 210258, 210202

Abstract:

The present invention discloses a desalination plant that operates with a sea water or brackish water feed and produces a concentrated and selectively improved salt reject stream and a pure water permeate stream from a first treatment section that is arranged to produce primarily water at high recovery using membrane desalination processes. The reject stream from the first treatment line has a component distribution that is substantially reduced in native di- and polyvalent scaling ions, essentially depleted of sulfate, has substantially higher total dissolved solids than a traditional sea water reverse osmosis reject, yet is suitable for thermal treatment processes. The system may be enhanced by monovalent salt components. The unit may be integrated with a second treatment section, in which the first reject stream is further concentrated, purified, and processed to produce a high purity salt product.

US Patent:

53717430, Dec 6, 1994

Filed:

Mar 6, 1992

Appl. No.:

7/847638

Inventors:

Joseph P. DeYesso - Walpole MA
Robert C. Solomon - Kensington NH
Stephen J. Todd - Shrewsbury MA
Mark C. Lippitt - Boulder CO

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 1100

US Classification:

371 81

Abstract:

A method for providing on-line replacement of a module which is at a specified position in an array of modules connected to a common control processor so that all other modules in the array can continue operating during the replacement operation. When the module is removed an indication is provided to the control processor showing that removal has occurred and identifying the position thereof. When the replacement has occurred an indication thereof is provided to the control processor, the replacement module is tested, and the state of the replacement module is updated to place it in the same state it would have been in if it had not been replaced.

US Patent:

61287504, Oct 3, 2000

Filed:

Jun 26, 1998

Appl. No.:

9/105064

Inventors:

James W. Espy - Andover MA
Scott Bleiweiss - Upton MA
Robert C. Solomon - Kensington NH
Brian K. Bailey - Shrewsbury MA
Peter Everdell - Littleton MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1100

US Classification:

714 7

Abstract:

A recovery method for use in a data storage system in which a plurality of data storage devices are connected to each of two communication paths. A switch may route requests to either of the two communication paths. With one data storage controller in communication with the data storage devices over a first path and a second data storage controller in communication with the data storage devices over a second path, upon detection of a malfunction on the first path, a data storage controller may request access to the other path. Thereafter, the controller may be switched into connection with the remaining operable path so as to share that path with the other controller.

US Patent:

61611654, Dec 12, 2000

Filed:

Mar 11, 1997

Appl. No.:

8/815193

Inventors:

Robert C. Solomon - Kensington NH
Brian K. Bailey - Shrewsbury MA
Robert Yates - Sutton MA
Peter Everdell - Littleton MA
Elizabeth H. Reeves - Westboro MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1200
G06F 1338

US Classification:

711114

Abstract:

A high performance data path for performing XOR on the fly. A first memory is connected to a first bus and a second memory is connected to a second bus selectively coupled to the first bus. Logic for performing an XOR can be switched into connection with the first and second bus for XORing data in a buffer with the data passed from one of the memories to the other memory. The result is replaced into the buffer to permit successive XORing. When reading from an interrelated group of disks such as a RAID 3 group, the data path permits an N-1 and go mode in which a read does not wait for data from the last disk to retrieve its data sector. If the last disk contains data (as opposed to parity) the data is obtained from the XORed data in the XOR buffer of the high performance data path. For writing data, the XOR on the fly generates the parity sector for writing at the completion of a write to an interrelated group of disks.