Robin W Edenfield

US Patent:

6535946, Mar 18, 2003

Filed:

Jan 4, 2000

Appl. No.:

09/477321

Inventors:

Christopher D. Bryant - Austin TX
Robin W. Edenfield - Dallas TX

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710305, 375354, 713400, 327141

Abstract:

There is disclosed, for use in an x86-compatible processor, an interface circuit for synchronizing the transfer of signals between different clock domains derived from a common core clock, where the phase and frequency relationships between the different domain clocks are known. The interface circuit comprises 1) a first latch having a data input for receiving a data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a second latch having a data input coupled to the first latch output, an enable input for receiving a gating signal, a clock input for receiving the first clock signal, and an output; 3) a third latch having a data input for receiving the data signal, an enable input for receiving a gating signal, a clock input for receiving the first clock signal, and an output; and 4) a multiplexer having a first data input coupled to the second latch output, a second data input coupled to the third latch output, and a selector input for selecting one of the first data input and the second data input for transfer to an output of the multiplexer.

US Patent:

6799280, Sep 28, 2004

Filed:

Jan 4, 2000

Appl. No.:

09/477488

Inventors:

Robin W. Edenfield - Dallas TX
Christopher D. Bryant - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04L 700

US Classification:

713400, 713410

Abstract:

An interface circuit is disclosed for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, where the phase and frequency relationships of the first and second clock signals are known. The interface circuit comprises: 1) a flip-flop having a data input for receiving a first data signal from the first clock domain, a clock input for receiving the first clock signal, and an output; 2) a latch having a data input coupled to the flip-flop output, a clock input for receiving a gating signal, and an output; and 3) a multiplexer having a first data input coupled to the flip-flop output, a second data input coupled to the latch output, and a selector input for selecting one of the first and second data inputs for the multiplexer output.