Sam N Tsai

age ~67

from Duarte, CA

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Sam Tsai Phones & Addresses

Non-Volatile And Reconfigurable Programmable Logic Devices
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US Patent:

6828823, Dec 7, 2004
Filed:

May 16, 2003
Appl. No.:

10/439602
Inventors:

Cyrus Tsui - Los Altos Hills CA
Benny Ma - Saratoga CA
Om P. Agrawal - Los Altos CA
Ju Shen - Saratoga CA
Sam Tsai - Milpitas CA
Jack Wong - Fremont CA
Chan-Chi Jason Cheng - Fremont CA
Assignee:

Lattice Semiconductor Corporation - Hillsboro OR
International Classification:

H03K 19177
US Classification:

326 40, 326 46
Abstract:

An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuits functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Dual-Port Sram With Bit Line Clamping
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US Patent:

8451679, May 28, 2013
Filed:

Aug 17, 2011
Appl. No.:

13/212121
Inventors:

Brad Sharpe-Geisler - San Jose CA, US
Timothy Scott Swensen - Santa Clara CA, US
Sam Tsai - Milpitas CA, US
Fabiano Fontana - San Jose CA, US
Assignee:

Lattice Semiconductor Corporation - Hillsboro OR
International Classification:

G11C 7/00
US Classification:

36523005, 36518906, 36518914, 365 1816
Abstract:

In one embodiment, a memory is provided that includes: a write driver for selectively driving a driven pair of bit lines selected from a plurality of bit line pairs during a write operation; a first stage clamping circuit operable to clamp a pair of internal nodes to a clamping voltage, wherein the first stage clamping circuit is further operable to unclamp the pair of internal nodes during the write operation; a bit line multiplexer for selectively coupling the driven bit line pair to the pair of internal nodes; and a second stage clamping circuit operable to clamp the plurality of bit line pairs to the clamping voltage, wherein the second stage clamping circuit is further operable to unclamp the driven bit line pair during the write operation.

Smartphone-Based Asset Management System
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US Patent:

20120202515, Aug 9, 2012
Filed:

Feb 9, 2011
Appl. No.:

13/023679
Inventors:

Cheng-Hsin Hsu - Mountain View CA, US
Jatinder Pal Singh - Mountain View CA, US
David M. Chen - Mountain View CA, US
Sam Tsai - Stanford CA, US
Bernd Girod - Stanford CA, US
Assignee:

STANFORD UNIVERSITY - Stanford CA
DEUTSCHE TELEKOM AG - Bonn
International Classification:

H04W 24/00
US Classification:

4554561
Abstract:

A method of tracking an inventory of objects via a mobile communications device includes acquiring an image of one or more of the objects via the mobile communications device, which also collects a location of the mobile communications device while acquiring the image of the one or more of the objects. The location and image are transferred from the mobile communications device to a remote server via a wireless network, such that the one or more of the objects are identified at the server based on the image, and the location and identity of the one or more objects are stored on a database associated with the server.

Dual-Port Sram With Bit Line Clamping
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US Patent:

20130258761, Oct 3, 2013
Filed:

May 24, 2013
Appl. No.:

13/901853
Inventors:

Timothy Scott Swensen - Santa Clara CA, US
Sam Tsai - Milpitas CA, US
Fabiano Fontana - San Jose CA, US
Assignee:

Lattice Semiconductor Corporation - Hillsboro OR
International Classification:

G11C 11/419
US Classification:

365154
Abstract:

In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.