Sanjiv K Mittal

US Patent:

20120130520, May 24, 2012

Filed:

Nov 17, 2011

Appl. No.:

13/299081

Inventors:

Suketu Arun Parikh - San Jose CA, US
Alexander T. Schwarm - Austin TX, US
Sanjiv Mittal - Fremont CA, US
Charles Gay - Westlake Village CA, US

International Classification:

G05B 19/418

US Classification:

700 96

Abstract:

A factory control server stores module configuration data for modules. The modules include processes for producing a final product and have corresponding module requirements. The factory control server analyzes in real-time actual product output data that is generated by a final product tester after a factory produces at least one final product to determine whether the actual product output data meets an expected product output. The factory control server analyzes actual module data in real-time to determine a new module requirement to cause new actual product output data for a subsequent final product to meet the expected product output in response to a determination that the actual product output data does not meet the expected product output. The factory control server notifies a module controller in real-time of the new module requirement. The module controller changes parameters in real-time to manufacture the subsequent final product.

US Patent:

47755504, Oct 4, 1988

Filed:

Jun 3, 1986

Appl. No.:

6/870234

Inventors:

John K. Chu - Fremont CA
Sanjiv K. Mittal - Fremont CA
John T. Orton - Pleasanton CA
Jagir S. Multani - Fremont CA
Robert Jecmen - Pleasanton CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

B05D 306
B05D 512

US Classification:

427 38

Abstract:

A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.

US Patent:

52798658, Jan 18, 1994

Filed:

Jun 28, 1991

Appl. No.:

7/722861

Inventors:

Robert P. Chebi - Austin TX
Sanjiv Mittal - Fremont CA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

B05D 306
B05D 314
C23C 1600

US Classification:

427574

Abstract:

Interlevel gaps between closely spaced circuit elements, such as closely spaced metal interconnect lines, are filed using a biased electron cyclotron resonance (ECR) deposition process. The gaps between circuit elements may be separated by distances of less than 0. 6 microns and the gaps can have aspect rations in excess of 2. To fill such gaps between the circuit elements on a semiconductor wafer, the wafer is mounted in an ECR reaction chamber. A continuing flow of oxygen (O. sub. 2) and silane (SiH. sub. 4) gas is introduced into the ECR system's plasma and reaction chambers, respectively, while applying a microwave excitation so as to generate a plasma. High deposition rates and low film stress are achieved by controlling the flow of oxygen and silane so as to maintain an oxygen to silane gas flow ratio of less than 1. 5. In addition, the wafer is cooled, typically using helium, so as to maintain wafer temperature below 300 degrees Celsius, because maintaining low temperatures during ECR deposition has been found to both increase the oxide deposition rate and to reduce the deposited film's compressive stress. This method makes it possible to achieve oxide deposition rates of 6000 Angstroms and above, with film stress below 1. 5. times. 10. sup.