Song S Zhao

US Patent:

6822297, Nov 23, 2004

Filed:

Jun 7, 2001

Appl. No.:

09/876292

Inventors:

Mahalingam Nandakumar - Richardson TX
Song Zhao - Dallas TX
Youngmin Kim - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257356, 257335, 257336, 257339, 257344, 257345, 257347, 257348, 257349, 257355, 257357, 257358, 257361, 257362, 458282, 458298, 458910

Abstract:

A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions. According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping. In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It , which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.

US Patent:

6855984, Feb 15, 2005

Filed:

Oct 30, 2003

Appl. No.:

10/697510

Inventors:

Zhiqiang Wu - Plano TX, US
Shaoping Tang - Plano TX, US
Song Zhao - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L029/76

US Classification:

257335, 257336, 257E21618

Abstract:

The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.

US Patent:

7029967, Apr 18, 2006

Filed:

Jul 21, 2004

Appl. No.:

10/896599

Inventors:

Song Zhao - Plano TX, US
Sue E. Crank - Coppell TX, US
Amitava Chatterjee - Plano TX, US
Kaiping Liu - Plano TX, US
Donald S. Miles - Plano TX, US
Duofeng Yue - Plano TX, US
Lance S. Robertson - Rockwall TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238
H01L 21/331

US Classification:

438199, 438223, 438230, 438369

Abstract:

A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.

US Patent:

7211481, May 1, 2007

Filed:

Feb 18, 2005

Appl. No.:

11/060841

Inventors:

Manoj Mehrotra - Plano TX, US
Lahir Shaik Adam - Plano TX, US
Song Zhao - Plano TX, US
Mahalingam Nandakumar - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238

US Classification:

438228, 438231, 438902, 257E2163

Abstract:

The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (). Subsequently, source/drain regions are formed in active regions of an NMOS region (). Then, a capped poly layer is formed over the device (). A second thermal process is performed () that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

US Patent:

7216310, May 8, 2007

Filed:

Nov 19, 2004

Appl. No.:

10/993815

Inventors:

Amitava Chatterjee - Plano TX, US
David Barry Scott - Plano TX, US
Theodore W. Houston - Richardson TX, US
Song Zhao - Plano TX, US
Shaoping Tang - Plano TX, US
Zhiqiang Wu - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50
G11C 5/14
H03K 3/01
G05F 1/10

US Classification:

716 2, 716 1, 716 4, 36518908, 365229, 327534, 327537

Abstract:

The present invention provides a method () of designing a circuit. The method comprises specifying () a design parameter for memory transistors and logic transistors and selecting () a test retention-mode bias voltage for the memory transistors. The method further comprises determining () a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining () a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used () to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting () the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

US Patent:

7678637, Mar 16, 2010

Filed:

Sep 12, 2008

Appl. No.:

12/209270

Inventors:

Mahalingam Nandakumar - Richardson TX, US
Song Zhao - Plano TX, US
Amitabh Jain - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238

US Classification:

438199, 438218, 438514, 438515, 438530

Abstract:

Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cmare achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

US Patent:

8101476, Jan 24, 2012

Filed:

Aug 14, 2009

Appl. No.:

12/541335

Inventors:

Kanan Garg - Plano TX, US
Haowen Bu - Plano TX, US
Mahalingam Nandakumar - Richardson TX, US
Song Zhao - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238

US Classification:

438199, 438792, 257E21293, 257E21634

Abstract:

A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.

US Patent:

8125035, Feb 28, 2012

Filed:

Jan 29, 2010

Appl. No.:

12/696215

Inventors:

Mahalingam Nandakumar - Richardson TX, US
Song Zhao - Plano TX, US
Amitabh Jain - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/092

US Classification:

257369, 257368, 257288, 257E27062

Abstract:

Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cmare achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.