Sreekanth Te Madgula
age ~53
from Folsom, CA
- Also known as:
-
- Sreekanth A Madgula
- Srevkandh Madgula
- Sreekanth Madaula
- Madgula Sreekanth
- Sreekanth A
- Phone and address:
- 1074 Smith Way, Folsom, CA 95630
Sreekanth Madgula Phones & Addresses
- 1074 Smith Way, Folsom, CA 95630
- Hutto, TX
- Rancho Cordova, CA
- Henderson, NV
- 3057 Sutter Buttes Dr, Roseville, CA 95747 • (916)4342752
- 1299 Antelope Creek Dr, Roseville, CA 95678 • (916)6388029
- Santa Clara, CA
- Sacramento, CA
- 1074 Smith Way, Folsom, CA 95630 • (916)8790448
Work
-
Company:Intel corporationJan 2009
-
Address:Folsom, CA, USA
-
Position:Technical lead/manager, soc hard ip group
Education
-
Degree:MS
-
School / High School:California State University-Sacramento
-
Specialities:Electrical Engineering
Skills
Timing Closure • Physical Design • Verilog • Cad • Design Methodology • Clock Tree Synthesis • Logic Synthesis • Perl • Shell Scripting • Cpu Design • Asic Design • Circuit Simulation • Circuit Optimization • Tcl • Unix • Eda Tool Evaluation • Vhdl • Synopsys Tools • Cadence Tools • Magma Tools • Eda Vendor Interface • Asic • Simulations • Soc • Eda • Vlsi • Static Timing Analysis • Rtl Design
Industries
Semiconductors
Resumes
Design Methodology Lead, Graphics Hardware Division
view sourceLocation:
1074 Smith Way, Folsom, CA 95630
Industry:
Semiconductors
Work:
Intel Corporation - Folsom, CA, USA since Jan 2009
Technical Lead/Manager, SoC Hard IP group
Intel Corporation - Folsom, CA, USA Sep 2004 - Dec 2008
Technical Lead/Manager, Chipset Division
Intel Corporation - Folsom, CA, USA Oct 2001 - Sep 2004
Design Automation Engineering Manager, CPU development group
Intel Corporation - Folsom, CA, USA Nov 1997 - Oct 2001
Senior CAD Engineer, CPU development group
Technical Lead/Manager, SoC Hard IP group
Intel Corporation - Folsom, CA, USA Sep 2004 - Dec 2008
Technical Lead/Manager, Chipset Division
Intel Corporation - Folsom, CA, USA Oct 2001 - Sep 2004
Design Automation Engineering Manager, CPU development group
Intel Corporation - Folsom, CA, USA Nov 1997 - Oct 2001
Senior CAD Engineer, CPU development group
Education:
California State University-Sacramento
MS, Electrical Engineering Jawaharlal Nehru Technological University
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering Stanford University
SCPD courses, Electrical Engineering
MS, Electrical Engineering Jawaharlal Nehru Technological University
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering Stanford University
SCPD courses, Electrical Engineering
Skills:
Timing Closure
Physical Design
Verilog
Cad
Design Methodology
Clock Tree Synthesis
Logic Synthesis
Perl
Shell Scripting
Cpu Design
Asic Design
Circuit Simulation
Circuit Optimization
Tcl
Unix
Eda Tool Evaluation
Vhdl
Synopsys Tools
Cadence Tools
Magma Tools
Eda Vendor Interface
Asic
Simulations
Soc
Eda
Vlsi
Static Timing Analysis
Rtl Design
Physical Design
Verilog
Cad
Design Methodology
Clock Tree Synthesis
Logic Synthesis
Perl
Shell Scripting
Cpu Design
Asic Design
Circuit Simulation
Circuit Optimization
Tcl
Unix
Eda Tool Evaluation
Vhdl
Synopsys Tools
Cadence Tools
Magma Tools
Eda Vendor Interface
Asic
Simulations
Soc
Eda
Vlsi
Static Timing Analysis
Rtl Design
Youtube
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