Stephen M Novak

US Patent:

6360305, Mar 19, 2002

Filed:

Dec 4, 1998

Appl. No.:

09/205456

Inventors:

Stephen T. Novak - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1336

US Classification:

711157, 711 5, 711105, 711111, 365203, 36523003, 36523008

Abstract:

A memory controller for a dynamic random access memory which pre-charges active banks in a particular chip select when an eight quadword access is made to another bank within that same chip select. When the memory controller detects an eight quadword access which is a page hit or page miss within the same chip select, the memory controller will look for any other active banks on that chip select. If there is another active bank other than the bank being accessed by the eight quadword access, the memory controller will attempt to transmit a pre-charge operation to that bank in the clock cycle immediately following the acceptance of the eight quadword access.

US Patent:

6496906, Dec 17, 2002

Filed:

Apr 30, 2001

Appl. No.:

09/846008

Inventors:

Stephen T. Novak - Sunnyvale CA
Scott Waldron - Belmont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711154, 711151, 711158, 711159, 365203, 370355

Abstract:

A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.

US Patent:

7149213, Dec 12, 2006

Filed:

May 16, 2002

Appl. No.:

10/147426

Inventors:

Stephan Rosner - Campbell CA, US
William F. Kern - Palo Alto CA, US
Ralf Flemming - Dresden-Radebeul, DE
Matthias Baer - Hohnstein Ernstthal, DE
Stephen T. Novak - Agoura CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04L 12/50

US Classification:

370379, 370392, 370474, 370476

Abstract:

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section ().

US Patent:

7313104, Dec 25, 2007

Filed:

May 16, 2002

Appl. No.:

10/147413

Inventors:

William F. Kern - Palo Alto CA, US
Stephan Rosner - Campbell CA, US
Ralf Flemming - Dresden-Radebeul, DE
Stephen T. Novak - Agoura CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04B 7/00
H04L 12/28
H04L 12/56
H04J 3/24

US Classification:

370310, 370412, 370474

Abstract:

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section (). Bus latencies are masked by at least overlapping transmitting the first portion of the transmit frame while downloading the second portion.

US Patent:

7729382, Jun 1, 2010

Filed:

Nov 1, 2006

Appl. No.:

11/591086

Inventors:

Stephan Rosner - Campbell CA, US
William F. Kern - Palo Alto CA, US
Ralf Flemming - Dresden-Radebeul, DE
Matthias Baer - Hohnstein Ernstthal, DE
Stephen T. Novak - Agoura CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04L 12/413

US Classification:

370474, 370476, 370445

Abstract:

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section ().

US Patent:

59268417, Jul 20, 1999

Filed:

Mar 13, 1996

Appl. No.:

8/614728

Inventors:

Stephen T. Novak - San Jose CA
Hong-Yi Chen - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1208

US Classification:

711208

Abstract:

A microprocessor having a segment descriptor cache that holds data obtained from a segment descriptor table contained in an external memory and a separate data cache that holds data obtained from portions of the external memory other than the segment descriptor table.

US Patent:

61479217, Nov 14, 2000

Filed:

Dec 16, 1999

Appl. No.:

9/464437

Inventors:

Stephen T. Novak - Sunnyvale CA
John C. Peck - San Francisco CA
Scott Waldron - Belmont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

365222

Abstract:

A memory controller for a dynamic random access memory having counters for each chip select in the memory. The counters are incremented at a fixed interval. Programmable threshold values are provided which, when compared with the counters, indicate to the memory controller when a refresh should be opportunistically attempted and when a refresh is urgently required. The memory controller then either attempts to find an idle cycle to send the opportunistic refresh or blocks memory accesses to create a window for an urgently needed refresh. Once a refresh is sent to the memory, the appropriate counter is decremented accordingly.

US Patent:

62955861, Sep 25, 2001

Filed:

Dec 4, 1998

Appl. No.:

9/205665

Inventors:

Stephen T. Novak - Sunnyvale CA
Scott Waldron - Belmont CA
John C. Peck - San Francisco CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711154

Abstract:

A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.