Steven A Meyers

US Patent:

6472915, Oct 29, 2002

Filed:

Sep 19, 2001

Appl. No.:

09/955865

Inventors:

Nathan Y. Moyal - Austin TX
Steven Meyers - Round Rock TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03L 706

US Classification:

327157

Abstract:

An apparatus comprising a phase lock loop (PLL) and a charge pump. The PLL may be configured to generate an output signal in response to an input signal. The charge pump may be configured within the PLL and be configured to (i) pump-up the input signal, (ii) pump-down the input signal or (iii) enter tri-state in response to a control signal.

US Patent:

6549050, Apr 15, 2003

Filed:

Sep 13, 2001

Appl. No.:

09/951369

Inventors:

Steven C. Meyers - Round Rock TX
Terry D. Little - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 3037

US Classification:

327217

Abstract:

A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.

US Patent:

6657472, Dec 2, 2003

Filed:

Apr 25, 2002

Appl. No.:

10/132857

Inventors:

S. Babar Raza - San Jose CA
Steven C. Meyers - Round Rock TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 3037

US Classification:

327217, 327225

Abstract:

The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.

US Patent:

6680632, Jan 20, 2004

Filed:

Feb 26, 2002

Appl. No.:

10/083442

Inventors:

Steven Meyers - Round Rock TX
Nathan Y. Moyal - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03L 706

US Classification:

327155, 327156

Abstract:

An apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.

US Patent:

7176737, Feb 13, 2007

Filed:

Jun 25, 2004

Appl. No.:

10/876730

Inventors:

Michael P. Baker - Round Rock TX, US
Steven C. Meyers - Round Rock TX, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03H 11/26

US Classification:

327280, 327158, 327266, 327274, 327287, 331 57

Abstract:

A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

US Patent:

7183822, Feb 27, 2007

Filed:

Aug 27, 2004

Appl. No.:

10/927979

Inventors:

Eric K. Bolton - Broomfield CO, US
Steven Meyers - Round Rock TX, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03L 7/06

US Classification:

327157

Abstract:

A charge pump circuit with resistively attenuated inputs is described herein. By reducing a voltage swing of input signals supplied thereto, the charge pump circuit described herein is configured for producing output signals with relatively low static phase offset even when operating at relatively low power supply voltages (e. g. , less than about 1. 2 volts). In general, the input voltage swing may be reduced by coupling an attenuator to each input of the charge pump circuit. A method for operating the differential charge pump is described, along with exemplary devices (e. g. , PLL and DLL devices) within which the charge pump may be utilized.

US Patent:

7199646, Apr 3, 2007

Filed:

Sep 14, 2004

Appl. No.:

10/940184

Inventors:

Dan Laurentiu Zupcau - Starkville MS, US
Steven Meyers - Round Rock TX, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G05F 3/24
G05F 3/26

US Classification:

327539, 323314, 323315

Abstract:

A bandgap circuit comprising a current generation circuit and a current replication circuit is provided herein. The output current of the current generation circuit is generated as a weighted sum of two currents. The circuit configuration of the current generation circuit allows it to function at low power supply voltages, e. g. , on the order of 1 V. The current replication circuit includes an operational amplifier, which when configured in conjunction with MOS cascode current sources and the current generation circuit, significantly increases the accuracy and insensitivity to power supply noise of the bandgap circuit output current. A resistor may be included between the bandgap circuit output node and ground for generating a reference voltage with increased accuracy and insensitivity to power supply noise.

US Patent:

20120206192, Aug 16, 2012

Filed:

Feb 15, 2011

Appl. No.:

13/027495

Inventors:

Jay B. Fletcher - Austin TX, US
Steven C. Meyers - Round Rock TX, US

International Classification:

G05F 1/10

US Classification:

327539

Abstract:

A bandgap reference circuit includes an amplifier configured to provide an output voltage dependent upon voltages appearing at an inverting input and a non-inverting input. The bandgap reference circuit also includes a first transistor coupled between the non-inverting input and a circuit ground reference, and a first resistor coupled to the inverting input. The bandgap reference circuit also includes a number of second transistors coupled in parallel between the circuit ground reference and the first resistor. At least a portion of the second transistors are connected to the first resistor through a plurality of programmably selectable switches.