Thomas H Huang

US Patent:

7353162, Apr 1, 2008

Filed:

Feb 11, 2005

Appl. No.:

11/056961

Inventors:

Thomas B. Huang - San Jose CA, US

Assignee:

S2C, Inc. - San Jose CA

International Classification:

G06F 9/455

US Classification:

703 23, 703 27, 703 20, 703 17, 714727, 714733, 714724, 716 17

Abstract:

A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customized or optimized third party circuits in an emulation using a platform including a number of field programmable devices. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design.

US Patent:

7908576, Mar 15, 2011

Filed:

Dec 10, 2007

Appl. No.:

11/953366

Inventors:

Thomas B. Huang - San Jose CA, US
Chioumin M. Chang - San Jose CA, US

Assignee:

INPA Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716106, 716107, 716111, 716112, 716124, 716136

Abstract:

A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes:.

US Patent:

8136065, Mar 13, 2012

Filed:

Apr 25, 2008

Appl. No.:

12/110233

Inventors:

Thomas B. Huang - San Jose CA, US
Chioumin M. Chang - San Jose CA, US

Assignee:

INPA Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716106, 716105, 716111, 716136

Abstract:

An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.

US Patent:

20100100860, Apr 22, 2010

Filed:

Oct 21, 2008

Appl. No.:

12/255606

Inventors:

Chioumin M. Chang - San Jose CA, US
Thomas B. Huang - San Jose CA, US
Huan-Chih Tsai - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716 5

Abstract:

Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment.

US Patent:

20100305933, Dec 2, 2010

Filed:

Jun 1, 2009

Appl. No.:

12/476012

Inventors:

Chioumin M. Chang - San Jose CA, US
Thomas B. Huang - San Jose CA, US
Huan-Chih Tsai - San Jose CA, US
Ting-Mao Chang - Hsin-Chu, TW

International Classification:

G06F 17/50

US Classification:

703 15

Abstract:

A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation.

US Patent:

20110289469, Nov 24, 2011

Filed:

May 21, 2010

Appl. No.:

12/785283

Inventors:

Thomas B. Huang - San Jose CA, US
Chioumin M. Chang - San Jose CA, US
Huan-Chih Tsai - San Jose CA, US
Ting-Mao Chang - Hsinchu City, TW

International Classification:

G06F 17/50

US Classification:

716125, 716126, 716137

Abstract:

A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuits each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique.

US Patent:

20120005547, Jan 5, 2012

Filed:

Jun 30, 2010

Appl. No.:

12/827917

Inventors:

Chioumin M. Chang - San Jose CA, US
Thomas B. Huang - San Jose CA, US
Huan-Chih Tsai - San Jose CA, US
Ting-Mao Chang - Hsinchu City, TW

International Classification:

G01R 31/3177
G06F 11/25

US Classification:

714734, 714E11155, 714724

Abstract:

A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller that controls programmable embedded debug circuits and transfers signal vectors between the built-in memories of the programmable embedded debug circuits and the vector processor interface bus; and (c) a vector processor which controls transferring of signal vectors between the host processor and the vector processor interface bus.

US Patent:

59406038, Aug 17, 1999

Filed:

Oct 17, 1997

Appl. No.:

8/953315

Inventors:

Thomas B. Huang - San Jose CA

Assignee:

Quickturn Design Systems, Inc. - Mountainview CA

International Classification:

G06F 300

US Classification:

395500

Abstract:

A memory design is implemented in static memory circuits having a plurality of bidirectional access ports, wherein each port is configured for read or write access. The memory design defines initial contents, depth, width, and bank selection in the memory circuits according to predefined configuration values, as well as, for each access port, whether that access port is configured for read or write. Port access occurs during time slots, which are based on external clock signals and memory circuit access times. Modified memory designs may be implemented such that access ports are accordingly reconfigured.