Thomas R Wik

US Patent:

6370078, Apr 9, 2002

Filed:

Dec 19, 2000

Appl. No.:

09/740604

Inventors:

Thomas R. Wik - Livermore CA
Ghasi R. Agrawal - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 800

US Classification:

36523005, 365 69, 365156

Abstract:

The present invention is directed to a system and method of compensating for coupling capacitance between bit lines in multi-port memories. The complementary bit lines are switched between a core cell and a modified core cell. The modified core cell may invert the connections to the access transistors. This results in the writing of data into the cell correctly while compensating for coupling capacitance.

US Patent:

6507524, Jan 14, 2003

Filed:

Nov 30, 2000

Appl. No.:

09/727043

Inventors:

Ghasi Agrawal - San Jose CA
Thomas R. Wik - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365200, 36523002, 36518902

Abstract:

A memory array has memory elements arranged in rows and columns. Each column has a respective bit line. A plurality of bit line input-output nodes are each switchably coupled to either a respective one of the bit lines or another one of the bit lines.

US Patent:

7557618, Jul 7, 2009

Filed:

Sep 24, 2007

Appl. No.:

11/903836

Inventors:

Thomas R. Wik - Livermore CA, US

International Classification:

H03K 19/20
H03K 19/094

US Classification:

326121, 327108

Abstract:

Conditioning logic modifies the electrical characteristics of conventional logic circuits to improve speed, power, and timing margins. This is accomplished by adding circuitry to pre-condition the state of the circuit to optimize any desired transition. Basic functionality of the logic circuit in response to the inputs is unchanged, but output delays, power dissipation, and timing margins can be improved and other characteristics of the circuit can also be controlled by the conditioning circuitry such as voltage levels, leakage current and power dissipation. The effect of the conditioning circuitry on the electrical and timing parameters of the logic function is controlled by binary feedback inputs to the conditioning circuitry. Feedback inputs can be generated from any combination of logic states and clock inputs including clock inputs and logic inputs not used in the logic function receiving the feedback input.

US Patent:

7603509, Oct 13, 2009

Filed:

Feb 6, 2008

Appl. No.:

12/069037

Inventors:

Thomas Robert Wik - Livermore CA, US

Assignee:

Adaptive Design Solutions, Inc. - Milpitas CA

International Classification:

G06F 13/42

US Classification:

710317, 710316

Abstract:

A crossbar switch is optimized for area, performance, and power by grouping the data lines that comprise the input ports and output ports of the switch into a plurality of separate cross-point blocks. Each cross-point block contains a complete set of input and output ports but the number of data lines comprising the input and output ports of each separate cross-point block is reduced to fraction of the number of data lines contained in each port of the crossbar switch. This fraction is equal to one divided by the number of separate cross-point blocks. Area, performance, and power of the crossbar switch are improved provided the area of the crossbar switch without grouping of data lines into separate cross-point blocks is determined by the pitch of the data lines rather than the area of the cross-point circuits. The number of blocks can be selected to optimize area, performance and power.

US Patent:

7746921, Jun 29, 2010

Filed:

Oct 11, 2006

Appl. No.:

11/546184

Inventors:

Thomas Robert Wik - Livermore CA, US

International Classification:

H04B 13/02

US Classification:

375218, 327108, 327111, 327110, 327 82, 327 83, 327168, 327382, 327389, 327 88

Abstract:

Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

US Patent:

20060218455, Sep 28, 2006

Filed:

Mar 23, 2005

Appl. No.:

11/089300

Inventors:

Kevin LeClair - Prior Lake MN, US
Thomas Wik - Livermore CA, US
Chuong Le - San Jose CA, US
Hieu Nguyen - San Jose CA, US
Duytan Tran - Los Gatos CA, US
Kevin Bligh - Ione CA, US

International Classification:

G01R 31/28

US Classification:

714726000

Abstract:

Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system testing includes setting a self-timed control input of the memory system to a predetermined self timed period value; and testing the memory based on the predetermined self timed period value.

US Patent:

58416951, Nov 24, 1998

Filed:

May 29, 1997

Appl. No.:

8/865470

Inventors:

Thomas R. Wik - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1602
G11C 1156

US Classification:

36518508

Abstract:

A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted.

US Patent:

58674233, Feb 2, 1999

Filed:

Apr 10, 1997

Appl. No.:

8/838799

Inventors:

Ashok Kapoor - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA
Raymond T. Leung - Palo Alto CA
V. Swamy Irrinki - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1156

US Classification:

365168

Abstract:

A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.