Trong D Nguyen

US Patent:

20130286751, Oct 31, 2013

Filed:

Apr 26, 2012

Appl. No.:

13/456217

Inventors:

Nitin Pant - New Delhi, IN
Trong D. Nguyen - Austin TX, US
Samaksh Sinha - Singapore, SG

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G11C 7/10
H03K 5/22

US Classification:

36518905, 327 65

Abstract:

A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.

US Patent:

59173564, Jun 29, 1999

Filed:

Sep 11, 1995

Appl. No.:

8/526395

Inventors:

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 300

US Classification:

327236

Abstract:

A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.

US Patent:

55240356, Jun 4, 1996

Filed:

Aug 10, 1995

Appl. No.:

8/513245

Inventors:

Humberto F. Casal - Austin TX
Rafey Mahmud - Austin TX
Trong Nguyen - Houston TX
Mark L. Shulman - Staatsburg NY
Nandor G. Thoma - Plano TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 2100

US Classification:

377 47

Abstract:

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

US Patent:

56191588, Apr 8, 1997

Filed:

Aug 18, 1995

Appl. No.:

8/516704

Inventors:

Humberto F. Casal - Austin TX
Joel R. Davidson - Austin TX
Hehching H. Li - Austin TX
Yuan C. Lo - Austin TX
Trong D. Nguyen - Webster TX
Campbell H. Snyder - Austin TX
Nandor G. Thoma - Plano TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 513

US Classification:

327292

Abstract:

A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock. The system provides dramatic simplification of replacement of either field replaceable units or individual components within field replaceable units. The system is self-phasing and self-correcting to accommodate timing misalignments caused by any variations in the timing delays at all levels, thereby reducing the jitter that must be accommodated.

US Patent:

56729910, Sep 30, 1997

Filed:

Apr 15, 1996

Appl. No.:

8/632184

Inventors:

Nandor Gyorgy Thoma - Plano TX
Trong Duc Nguyen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03H 1116

US Classification:

327239

Abstract:

A signal delay device is provided which enhances noise immunity by using a differential circuit, but also maintains the phase of the input clock signals. This device will also correct the phase of clock signals which are input to the delay device in an out of phase condition. The present invention is a delay circuit that includes functionally connecting each of the output signals with each of the input signals. Thus, the output signals are dependent on the same input and the steady state condition is the point where the leading edge of a first output signal intersects the trailing edge of a second output signal at the point which corresponds to one half of the pulse height of both signals. Since the signals are complements of one another, they will cross at 50% of their pulse height when they are "in phase". Thus, the present invention will maintain "in phase" input signals and seek an "in phase" condition for signals that are input to the delay circuit which are "out of phase".

US Patent:

58225960, Oct 13, 1998

Filed:

Nov 6, 1995

Appl. No.:

8/554206

Inventors:

Humberto Felipe Casal - Austin TX
Hehching Harry Li - Austin TX
Trong Duc Nguyen - Webster TX
Nandor Gyorgy Thoma - Plano TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 2100
G06F 1300

US Classification:

39575004

Abstract:

During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

US Patent:

20210224544, Jul 22, 2021

Filed:

Apr 9, 2021

Appl. No.:

17/226405

Inventors:

- Irving TX, US
Sailesh Bharathwaaj Krishnamurthy - Irving TX, US
Trong Nghia Nguyen - Dallas TX, US

International Classification:

G06K 9/00
G06T 7/292
H04N 7/18
G06T 7/246

Abstract:

A system includes sensors and a tracking subsystem. The subsystem receives frames of top-view images generated by the sensors. The subsystem tracks a first and second object, based on received frames. The subsystem detects that the first object is within a threshold distance of the second object. In response, the subsystem determines a probability that the first object switched identifiers with the second object and updates candidate lists accordingly for the first and second objects. The updated first candidate list includes a probability that the first object is associated with a first identifier and a probability that the first object is associated with a second identifier.

US Patent:

20210124921, Apr 29, 2021

Filed:

Jul 24, 2020

Appl. No.:

16/938676

Inventors:

- Irving TX, US
Sailesh Bharathwaaj Krishnamurthy - Irving TX, US
Trong Nghia Nguyen - Dallas TX, US
Sarath Vakacharla - Irving TX, US

International Classification:

G06K 9/00
G06Q 30/06
G06N 20/00

Abstract:

An apparatus includes a processor. The processor receives an algorithmic shopping cart that includes a first set of items determined by an algorithm to have been selected by a person during a shopping session in a physical store, based on a set of inputs received from sensors located within the physical store. The processor also receives a virtual shopping cart that includes a second set of items. Video of the shopping session was captured by a set of cameras located in the physical store and depicts the person selecting the second set of items. The processor compares the algorithmic cart to the virtual cart and determines that a discrepancy exists between the algorithmic cart and the virtual cart. The processor determines a subset of the set of inputs associated with the discrepancy and attaches metadata explaining the discrepancy to the subset. The processor uses the subset to train the algorithm.

Address:

7520 Arbor Park Dr, Fort Worth, TX 76120

Phone:

(817)2965518

VIN:

WDDHF5GB4BA500980

Make:

MERCEDES-BENZ

Model:

E-CLASS

Year:

2011