Trung Van Nguyen

US Patent:

8055934, Nov 8, 2011

Filed:

Jun 22, 2010

Appl. No.:

12/820779

Inventors:

Stephen LaRoux Blinick - Tucson AZ, US
Scott Alan Brewer - Tucson AZ, US
Trung Ngoc Nguyen - Tucson AZ, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 411, 714 412, 714 51, 714 10

Abstract:

In one aspect of the present description, in response to detection of a failure of a root server of a storage controller, a switch for input/output adapters may be reconfigured to report errors to a successor root server without reinitializing the input/output adapters. Other features and aspects may be realized, depending upon the particular application.

US Patent:

20140082629, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/616930

Inventors:

Kevin John ASH - Tucson AZ, US
Michael Thomas BENHASE - Tucson AZ, US
Lokesh Mohan GUPTA - Tucson AZ, US
Trung Ngoc NGUYEN - Tucson AZ, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/46

US Classification:

718105

Abstract:

A set of like tasks to be performed is organized into a first group. Upon a determined imbalance between dispatch queue depths greater than a predetermined threshold, the set of like tasks is reassigned to an additional group.

US Patent:

20140082631, Mar 20, 2014

Filed:

Nov 7, 2013

Appl. No.:

14/074307

Inventors:

Michael T. BENHASE - Tucson AZ, US
Lokesh M. GUPTA - Tucson AZ, US
Trung N. NGUYEN - Tucson AZ, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/50

US Classification:

718105

Abstract:

A set of like tasks to be performed is organized into a first group. Upon a determined imbalance between dispatch queue depths greater than a predetermined threshold, the set of like tasks is reassigned to an additional group.

US Patent:

20210263781, Aug 26, 2021

Filed:

Feb 22, 2020

Appl. No.:

16/798339

Inventors:

- Armonk NY, US
Matthew J. Kalos - Tucson AZ, US
Kevin J. Ash - Tucson AZ, US
Trung N. Nguyen - Vail AZ, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/50
G06F 9/48

Abstract:

A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.

US Patent:

20210157635, May 27, 2021

Filed:

Nov 21, 2019

Appl. No.:

16/690131

Inventors:

- Armonk NY, US
Lokesh M. Gupta - Tucson AZ, US
Kevin J. Ash - Tucson AZ, US
Matthew J. Kalos - Tucson AZ, US
Trung N. Nguyen - Vail AZ, US
Clint A. Hardy - Tucson AZ, US
Louis A. Rasor - Tucson AZ, US

International Classification:

G06F 9/48
G06F 9/50
G06F 9/52
G06F 13/20

Abstract:

Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.

US Patent:

20210149801, May 20, 2021

Filed:

Nov 19, 2020

Appl. No.:

16/953046

Inventors:

- Armonk NY, US
Matthew G. Borlick - Tucson AZ, US
Lokesh M. Gupta - Tucson AZ, US
Trung N. Nguyen - Vail AZ, US

International Classification:

G06F 12/0804
G06F 12/121
G06F 12/0868

Abstract:

In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

US Patent:

20210073050, Mar 11, 2021

Filed:

Sep 11, 2019

Appl. No.:

16/567932

Inventors:

- Armonk NY, US
Lokesh M. Gupta - Tucson AZ, US
Trung N. Nguyen - Vail AZ, US
Seamus Burke - Tucson AZ, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/52
G06F 9/48
G06F 3/06

Abstract:

A method is disclosed to reduce lock contention in a data storage system. The method dispatches, on a first processor core, a task configured to acquire a lock on a data storage resource, such as memory. The method then determines whether the first processor core is associated with the data storage resource. If the first processor core is not associated with the data storage resource, the method re-dispatches the task on a second processor core that is associated with the data storage resource. In certain embodiments, the task is only re-dispatched on the second processor core if an amount of effort required to acquire the lock is above a selected threshold. If, on the other hand, the first processor core is associated with the data storage resource, the method executes the task on the first processor core. A corresponding system and computer program product are also disclosed.

US Patent:

20210073090, Mar 11, 2021

Filed:

Sep 11, 2019

Appl. No.:

16/568105

Inventors:

- Armonk NY, US
Sean Patrick Riley - Tucson AZ, US
Brian Anthony Rinaldi - Tucson AZ, US
Trung N. Nguyen - Vail AZ, US
Lokesh M. Gupta - Tucson AZ, US

International Classification:

G06F 11/20
G06F 9/445
H04L 29/08

Abstract:

A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.