Vinh Thiem Diep

US Patent:

20110163642, Jul 7, 2011

Filed:

Jan 6, 2010

Appl. No.:

12/683328

Inventors:

Matthew D. Rohrbach - San Francisco CA, US
Vinh Diep - Milpitas CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

A47B 81/00
B23P 11/00

US Classification:

3122231, 29428

Abstract:

This is directed to a case for securing and protecting an electronic device. The case can include a cover connected to a pouch by a hinge such that the cover can be overlaid over a device interface (e.g., a device display). The case can be constructed by layering and combining several types of materials, including for example materials having resistant outer surfaces, materials limiting the deformation of the case, materials providing a soft surface to be placed in contact with the device, and rigid materials for defining a structure of the case. In some embodiments, the case can include a tab that allows a user to fold open the cover of the case to form a triangular prism. The prism can be placed on any of its surfaces such that the device can be oriented towards a user at particular angles (e.g., a typing-specific orientation and a media playback orientation).

US Patent:

20130050943, Feb 28, 2013

Filed:

Aug 30, 2011

Appl. No.:

13/221796

Inventors:

Vinh Diep - Palo Alto CA, US
Chiew-Siang Goh - San Jose CA, US
Doug Heirich - Palo Alto CA, US
Alexander Michael Kwan - Los Altos Hills CA, US

International Classification:

H05K 7/20

US Classification:

361702

Abstract:

An electronic device may have a housing in which electronic components are mounted. The electronic components may be mounted to a substrate such as a printed circuit board. A heat sink structure may dissipate heat generated by the electronic components. The housing may have a housing wall that is separated from the heat sink structure by an air gap. The housing wall may have integral support structures. Each of the support structures may have an inwardly protruding portion that protrudes through a corresponding opening in the heat sink structure. The protruding portions may each have a longitudinal axis and a cylindrical cavity that lies along the longitudinal axis. Each of the support structures may have fins that extend radially outward from the longitudinal axis.

US Patent:

20130050945, Feb 28, 2013

Filed:

Aug 31, 2011

Appl. No.:

13/223030

Inventors:

Vinh Diep - Palo Alto CA, US
Dominic Dolci - Berkeley CA, US
Chiew-Siang Goh - San Jose CA, US
Alexander Michael Kwan - Los Altos Hills CA, US
Cesar Lozano Villarreal - Sunnyvale CA, US

International Classification:

H05K 5/00
H05K 5/02
A47B 87/00
H05K 7/20

US Classification:

361704, 361807, 361752, 312111

Abstract:

An electronic device may have electronic device housing structures in which electronic components such as integrated circuits and connectors may be mounted. The electronic device housing structures may include an upper housing having a planar upper surface member and four perpendicular housing sidewall structures. The housing sidewall structures of the upper housing may have edges that form a rectangular opening with curved corners. A lower housing may have structures forming a rectangular lip that is configured to be received within the rectangular opening in the upper housing. Engagement structures such as inwardly protruding hook structures on the upper housing and snap structures on the rectangular lip may be used in attaching the upper and lower housings. The snap structures may each have a rectangular main opening and lateral extension portions that extend the width of the main opening along the edge of the lip.

US Patent:

20140078677, Mar 20, 2014

Filed:

Sep 20, 2012

Appl. No.:

13/623436

Inventors:

Dominic E. Dolci - Berkeley CA, US
James G. Smeenge - Los Gatos CA, US
Vinh H. Diep - Palo Alto CA, US
Chiew-Siang Goh - San Jose CA, US

International Classification:

H05K 7/20
H05K 9/00

US Classification:

361719, 361704, 361718, 361720

Abstract:

An electronic device may be provided with electronic components such as radio-frequency transceiver integrated circuits and other integrated circuits that are be sensitive to electromagnetic interference. Metal structures are configured to serve both as heat sinking structures for the electrical components and electromagnetic interference shielding. Components are mounted to the substrate using solder. Metal fence structures are also soldered to the substrate. Each metal fence has an opening that covers a respective one of the components. A thermally conductive elastomeric gap filler pad is mounted in the opening. A metal heat spreading structure is electrically shorted to the fence using a conductive gasket that surrounds the gap filler pad so that the structure serves as an electromagnetic interference shield. Heat from the component travels through the gap filler pad to the metal heat spreading structure so that the heat spreading structure may laterally spread and dissipate the heat.

US Patent:

20220199175, Jun 23, 2022

Filed:

Mar 2, 2021

Appl. No.:

17/249433

Inventors:

- Boise ID, US
Vinh Q. Diep - Hayward CA, US
Zhengyi Zhang - San Jose CA, US
Yingda Dong - Los Altos CA, US

International Classification:

G11C 16/34
G11C 16/30
G11C 16/10
G11C 16/08

Abstract:

Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

US Patent:

20230044240, Feb 9, 2023

Filed:

Oct 20, 2022

Appl. No.:

17/970459

Inventors:

- Boise ID, US
Vinh Q. Diep - Hayward CA, US
Zhengyi Zhang - San Jose CA, US
Yingda Dong - Los Altos CA, US

International Classification:

G11C 16/34
G11C 16/08
G11C 16/10
G11C 16/30

Abstract:

Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

US Patent:

20200312414, Oct 1, 2020

Filed:

Jun 12, 2020

Appl. No.:

16/900015

Inventors:

- Addison TX, US
Ching-Huang Lu - Fremont CA, US
Vinh Diep - San Jose CA, US
Yingda Dong - Los Altos CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G11C 16/34
G11C 16/26
G11C 16/24
G11C 16/10
G11C 11/56

Abstract:

Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

US Patent:

20200211663, Jul 2, 2020

Filed:

Dec 27, 2018

Appl. No.:

16/233723

Inventors:

- Addison TX, US
Ching-Huang Lu - Fremont CA, US
Vinh Diep - San Jose CA, US
Yingda Dong - Los Altos CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G11C 16/34
G11C 16/10
G11C 11/56
G11C 16/24
G11C 16/26

Abstract:

Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.