Vuong Kim Nguyen

US Patent:

7853735, Dec 14, 2010

Filed:

Dec 13, 2007

Appl. No.:

11/956262

Inventors:

Daming Jin - Costa Mesa CA, US
Joe Chung-Ping Tien - Costa Mesa CA, US
Michael P. Yan - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 5/00

US Classification:

710 39, 710 5, 710 22, 711202

Abstract:

This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.

US Patent:

7937188, May 3, 2011

Filed:

May 23, 2007

Appl. No.:

11/805581

Inventors:

Michael Yu Liu - Costa Mesa CA, US
Bradley Eugene Roach - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US
Peter Mark Fiacco - Costa Mesa CA, US
Shak Loong Kwok - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 15/00

US Classification:

700299, 710 10, 702132, 713300, 709221

Abstract:

Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.

US Patent:

8111696, Feb 7, 2012

Filed:

Oct 14, 2008

Appl. No.:

12/251290

Inventors:

Vuong Cao Nguyen - Costa Mesa CA, US
Steven Gerard Lemire - Costa Mesa CA, US
Raul Bersamin Oteyza - Costa Mesa CA, US
Jeff Junwei Zheng - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

H04L 12/28

US Classification:

370392, 370388, 370349

Abstract:

A method is disclosed for indicating a status of a transfer of data from a first device to a second device over a network. In one embodiment, the data includes one or more data frames. Each frame includes a header having one or more bits. The method includes setting a last bit of the one or more bits in the header of a last frame of the one or more data frames to a first value if the status of the transfer of data is good and setting the value of the last bit of the last data frame to a second value if the transfer of data failed. This results in a less congested, more efficient network.

US Patent:

8631169, Jan 14, 2014

Filed:

Jun 6, 2008

Appl. No.:

12/134985

Inventors:

Daming Jin - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US
Sam Shan-Jan Su - Costa Mesa CA, US
John Sui-Kei Tang - Costa Mesa CA, US
Peter Mark Fiacco - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/28

US Classification:

710 22

Abstract:

Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.

US Patent:

20090172287, Jul 2, 2009

Filed:

Dec 28, 2007

Appl. No.:

11/966900

Inventors:

Steven Gerard LeMIRE - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US

International Classification:

G06F 12/08

US Classification:

711128, 711E12018

Abstract:

Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

US Patent:

20120092354, Apr 19, 2012

Filed:

Aug 25, 2011

Appl. No.:

13/218049

Inventors:

Daniel Aghassian - Glendale CA, US
Thomas Stouffer - Chatsworth CA, US
Vuong Nguyen - Glendale CA, US

Assignee:

Boston Scientific Neuromodulation Corporation - Valencia CA

International Classification:

G06T 1/00

US Classification:

345522

Abstract:

An improved external controller with dual microcontrollers useable with an implantable medical device is disclosed. The external controller comprises a low speed (low frequency) microcontroller and a high speed (high frequency) microcontroller. The low speed microcontroller receives telemetry data from the medical device, converts data into graphical commands, and transmits commands to the high speed microcontroller. The high speed microcontroller interprets the graphical commands, retrieves images indicative of the commands from a storage device, and renders the images onto a display screen. The high speed microcontroller may also process more complicated data sent from the low speed microcontroller, and return the results to the low speed microcontroller to allow it to form the graphics command for the high speed microcontroller to execute.

US Patent:

20190324926, Oct 24, 2019

Filed:

Apr 19, 2018

Appl. No.:

15/957264

Inventors:

- Singapore, SG
Mark Karnowski - Huntington Beach CA, US
James Smart - Laguna Hills CA, US
Ravi Shenoy - Sunnyvale CA, US
Lalit Chhabra - Fremont CA, US
Gregorio Gervasio, JR. - Santa Clara CA, US
Tuong Le - Irvine CA, US
Vuong Nguyen - Aliso Viejo CA, US

International Classification:

G06F 13/16
G06F 13/42

Abstract:

A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.

US Patent:

20150378923, Dec 31, 2015

Filed:

Aug 26, 2015

Appl. No.:

14/835936

Inventors:

- Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US

International Classification:

G06F 12/08

Abstract:

Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.