Wayne H Huang

US Patent:

8226772, Jul 24, 2012

Filed:

Jan 8, 2009

Appl. No.:

12/350789

Inventors:

Neil Joseph Greeley - Boise ID, US
Dan Millward - Boise ID, US
Wayne Huang - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B08B 3/04

US Classification:

134 13, 134 1, 134 33, 134 34

Abstract:

Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

US Patent:

8633084, Jan 21, 2014

Filed:

Oct 17, 2012

Appl. No.:

13/654258

Inventors:

Beth R. Cook - Meridian ID, US
Lei Bi - Boise ID, US
Wayne Huang - Boise ID, US
Ian C. Laboriante - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/20

US Classification:

438381, 257E21396

Abstract:

A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

US Patent:

20090239379, Sep 24, 2009

Filed:

Mar 24, 2008

Appl. No.:

12/054077

Inventors:

Wayne Huang - Boise ID, US
Whonchee Lee - Boise ID, US

International Classification:

H01L 21/306

US Classification:

438692, 257E2123

Abstract:

A method of removing a material from a surface includes providing a substrate comprising a material having a surface, contacting the surface with a polishing medium, applying a voltage to the substrate to remove material from the surface, and changing the voltage during the removing material from the surface. An electrochemical mechanical polishing method includes providing a substrate having a surface, applying a platen to the surface, applying a first voltage to the substrate, rotating the platen and surface relative to each other at a first rotational speed, increasing to a second voltage, and decreasing to a second rotational speed.

US Patent:

20120266913, Oct 25, 2012

Filed:

Jun 27, 2012

Appl. No.:

13/535322

Inventors:

Neil Joseph Greeley - Boise ID, US
Dan Millward - Boise ID, US
Wayne Huang - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

B08B 3/10

US Classification:

134 13

Abstract:

Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.

US Patent:

20130313718, Nov 28, 2013

Filed:

May 24, 2012

Appl. No.:

13/480341

Inventors:

Sony Varghese - Boise ID, US
Andrew Carswell - Boise ID, US
Kozaburo Sakai - Boise ID, US
Andrey V. Zagrebelny - Eagan MN, US
Wayne Huang - Boise ID, US
Jin Lu - Boise ID, US
Suresh Ramakrishnan - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 23/498
H01L 21/66
H01L 21/768

US Classification:

257774, 438667, 438 16, 257E23067, 257E2153, 257E21577

Abstract:

A method of processing a substrate having integrated circuitry includes forming through-substrate vias partially through the substrate from a first side of the substrate. At least one through-substrate structure is formed partially through the substrate from the first substrate side. The at least one through-substrate structure extends deeper into the substrate than do the through-substrate vias. Substrate material is removed from a second side of the substrate to expose the through-substrate vias and the at least one through-substrate structure on the second substrate side. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

US Patent:

20140004698, Jan 2, 2014

Filed:

Jun 29, 2012

Appl. No.:

13/538272

Inventors:

Wayne H. Huang - Boise ID, US
Anurag Jindal - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 21/28

US Classification:

438653, 438672, 438667, 257E21158

Abstract:

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.

US Patent:

20210343670, Nov 4, 2021

Filed:

Jul 15, 2021

Appl. No.:

17/376934

Inventors:

- Boise ID, US
Owen R. Fay - Meridian ID, US
Sameer S. Vadhavkar - Boise ID, US
Adriel Jebin Jacob Jebaraj - Boise ID, US
Wayne H. Huang - Boise ID, US

International Classification:

H01L 23/00

Abstract:

A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

US Patent:

20210166996, Jun 3, 2021

Filed:

Feb 12, 2021

Appl. No.:

17/175006

Inventors:

- Boise ID, US
Wayne H. Huang - Boise ID, US
Sameer S. Vadhavkar - Boise ID, US

International Classification:

H01L 23/48
H01L 23/00
H01L 25/065
H01L 21/683

Abstract:

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

Address:

9905 W Countryman Dr, Boise, ID 83709

Phone:

(208)3424168

VIN:

JTEHW21A670042215

Make:

TOYOTA

Model:

HIGHLANDER HYBRID

Year:

2007