Wilson Wong - San Francisco CA, US Allen Chan - San Jose CA, US Weiqi Ding - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/00
US Classification:
331 2, 331 49, 331 16, 327147, 327156
Abstract:
A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL.
Wilson Wong - San Francisco CA, US Allen Chan - San Jose CA, US Thungoc M. Tran - San Jose CA, US Tim Tri Hoang - San Jose CA, US Weiqi Ding - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 19/00
US Classification:
702189
Abstract:
Signal detection circuitry for a serial interface oversamples the input—i. e. , samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
Configurable Emphasis For High-Speed Transmitter Driver Circuitry
Pre-emphasis may be able to operate in either of two modes. In a first mode, when one bit has a same value as the bit that immediately preceded it, an output signal for said one bit is based on a first electrical current reduced by a second electrical current. Otherwise the output signal for said one bit is based on the first current without regard for the second current. The second mode may be similar to the first mode when said one bit has the same value as the immediately preceding bit; but otherwise the output signal for said one bit is based on the first current increased by the second current. As an alternative to using the immediately preceding bit (as in the above “post-tap” operation), the immediately succeeding (following) bit may be used in generally the same way (in so-called “pre-tap” operation).
Process/Design Methodology To Enable High Performance Logic And Analog Circuits Using A Single Process
Qi Xiang - San Jose CA, US Albert Ratnakumar - San Jose CA, US Jeffrey Xiaoqi Tung - Milpitas CA, US Weiqi Ding - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G05F 1/10
US Classification:
327535, 327534
Abstract:
A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
High-Frequency Low-Gain Ring Vco For Clock-Data Recovery In High-Speed Serial Interface Of A Programmable Logic Device
Weiqi Ding - Fremont CA, US Mengchi Liu - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03B 5/12
US Classification:
331 17, 331177 V, 331179, 331 8, 331 1 R
Abstract:
A voltage-controlled oscillator operates at high frequency without high gain by dividing the frequency range into a plurality of subranges, which preferably are substantially equal in size. Within any subrange, the full extent of variation in the control signal changes the frequency only by the extent of the subrange. The gain is thus substantially equal to the gain one would expect for the full frequency range, divided by the number of subranges. The subrange may be selected manually, or by an initial calibration process. In one embodiment, the oscillator includes a voltage-to-current converter and a current-controlled oscillator, with a current mirror arrangement. In that embodiment, selection of the subrange may be controlled by turning on the correct number of current legs.
A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to generate a pull-down signal. The inverter comprises complementary transistors that receive charge from the supply voltage. The pull-up circuit pulls a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal. The pull-down circuit pulls the level shifted output signal to a low voltage in response to the pull-down signal.
Serial Data Signal Eye Width Estimator Methods And Apparatus
Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e. g. , until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.
On-Chip Data Signal Eye Monitoring Circuitry And Methods
Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.