Wilman Te Tsai

US Patent:

6458495, Oct 1, 2002

Filed:

Jun 29, 2000

Appl. No.:

09/607446

Inventors:

Wilman Tsai - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

The present invention comprises a phase-shifting mask and a process for fabricating such a phase-shifting mask. The phase-shifting mask has trenches with vertical sidewall profiles which are retrograde. The retrograde profiles balance the transmission and phase of the light transmitted through the phase-shifted openings relative to the non-phase-shifted openings. The retrograde profile may be formed from an isotropic plasma etch.

US Patent:

6485869, Nov 26, 2002

Filed:

Oct 1, 1999

Appl. No.:

09/411729

Inventors:

Wilman Tsai - Saratoga CA
Marilyn Kamna - San Jose CA
Frederick Chen - San Jose CA
Jeff Farnsworth - Los Gatos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.

US Patent:

6692878, Feb 17, 2004

Filed:

Aug 15, 2002

Appl. No.:

10/222655

Inventors:

Wilman Tsai - Saratoga CA
Marilyn Kamna - San Jose CA
Frederick Chen - San Jose CA
Jeff Farnsworth - Los Gatos CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5, 355 18

Abstract:

An apparatus comprising a mask having an active device area and a moat. The moat substantially surrounds the mask active device area and has a width greater than a plasma specie diffusional length. A method comprising depositing a layer of resist on a mask substrate having transparent and opaque layers; and exposing the resist layer to radiation. The radiation is patterned to produce features within an active device area. The radiation is also patterned to produce a moat substantially surrounding the active device area having a width greater than a plasma specie diffusional length.

US Patent:

7208366, Apr 24, 2007

Filed:

Aug 12, 2004

Appl. No.:

10/917886

Inventors:

Wilman Tsai - Saratoga CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8238

US Classification:

438216, 438287, 438591, 438785

Abstract:

A technique for producing a thin gate oxide having a relatively high dielectric constant. Embodiments relate to the structure and development of a gate oxide having a thickness of less than 1 nm, having a dielectric constant greater than twenty, and being substantially free of undesired electrical characteristics caused by exposure of the gate oxide to high complementary metal-oxide-semiconductor processing temperatures.

US Patent:

7435987, Oct 14, 2008

Filed:

Mar 27, 2007

Appl. No.:

11/728890

Inventors:

Chi On Chui - Los Angeles CA, US
Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack T. Kavalieros - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31/0328

US Classification:

257 14, 257 19, 257194, 257E29069, 257E29072

Abstract:

In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (SiGe), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (SiGe(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of SiGe(C). Other embodiments are described and claimed.

US Patent:

7629603, Dec 8, 2009

Filed:

Jun 9, 2006

Appl. No.:

11/450744

Inventors:

Chi On Chui - San Mateo CA, US
Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack T. Kavalieros - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31/00

US Classification:

257 18, 257254, 257417, 257E29193, 257213

Abstract:

A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

US Patent:

7763511, Jul 27, 2010

Filed:

Dec 29, 2006

Appl. No.:

11/618666

Inventors:

Prashant Majhi - Austin TX, US
Kyu S. Min - San Jose CA, US
Wilman Tsai - Saratoga CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438257, 438260, 438710

Abstract:

Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.

US Patent:

7777282, Aug 17, 2010

Filed:

Aug 13, 2008

Appl. No.:

12/228457

Inventors:

Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack Kavalieros - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Benjamin Chu-Kung - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76
H01L 29/94

US Classification:

257401, 257404, 257E29179

Abstract:

A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.