Wing Ming Leung

US Patent:

6425046, Jul 23, 2002

Filed:

Mar 18, 1997

Appl. No.:

08/820297

Inventors:

Wing Yu Leung - Cupertino CA
Fu-Chieh Hsu - Saratoga CA

Assignee:

Monolithic System Technology, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

711101, 711118, 357 51, 357 57, 257907, 36523008, 365196, 365210

Abstract:

A fault-tolerant, high-speed wafer scale system includes a plurality of functional memory modules, each having associated sense amplifiers which act as high-speed cache memory, a parallel hierarchical bus which is fault-tolerant to defects and a interconnect network, and one or more bus masters. By grouping the DRAM arrays into logically independent modules of relatively small memory capacity (588 Kbit), a large number of cache lines ( ) is obtained at small main memory capacity (4 Megabytes). The large number of cache lines allows maintaining a high cache hit rate (greater than 90%).

US Patent:

6483755, Nov 19, 2002

Filed:

Jul 10, 2001

Appl. No.:

09/903094

Inventors:

Wing Yu Leung - Cupertino CA
Fu-Chieh Hsu - Saratoga CA

Assignee:

Monolithic System Technology, Inc. - Sunnyvale CA

International Classification:

G06F 1208

US Classification:

36518905, 711 5, 711101, 711118, 36518508, 36523008

Abstract:

A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained; and 10) use of sense amplifiers already associated with memory arrays as high speed (cache) memory.

US Patent:

6717864, Apr 6, 2004

Filed:

Oct 15, 2002

Appl. No.:

10/273442

Inventors:

Wing Yu Leung - Cupertino CA
Fu-Chieh Hsu - Saratoga CA

Assignee:

Monlithic System Technology, Inc. - Sunnyvale CA

International Classification:

G06F 1208

US Classification:

36518905, 36518508, 36523008, 711 5, 711101, 711118

Abstract:

A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system.

US Patent:

6781885, Aug 24, 2004

Filed:

Mar 5, 2003

Appl. No.:

10/379885

Inventors:

Sheung Hee Park - Santa Clara CA
Richard Fastow - Cupertino CA
Wing Han Leung - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1134

US Classification:

36518528, 36518522

Abstract:

In programming the threshold voltage of a memory cell transistor having a substrate, a gate insulator on the substrate, a floating gate on the gate insulator, an insulating layer on the floating gate, and a control gate on the insulating layer, and a source and drain in the substrate, a voltage difference is applied between the drain and source of the transistor and negative voltage is applied to the substrate of the transistor. An increasing voltage is applied to the control gate of the transistor, and, during application of that increasing voltage, a succession of verification tests are undertaken at a corresponding succession of times separated by chosen time intervals to verify if the transistor has been programmed to a chosen threshold voltage.

US Patent:

6819615, Nov 16, 2004

Filed:

Oct 31, 2002

Appl. No.:

10/285909

Inventors:

Richard M. Fastow - Cupertino CA
Wing Han Leung - Sunnyvale CA
John Wang - San Jose CA

Assignee:

Advanced Micro Device, Inc. - Sunnyvale CA

International Classification:

G11C 702

US Classification:

365210, 3651852, 36518526, 36518529, 365226

Abstract:

A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the I versus V curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.

US Patent:

6937518, Aug 30, 2005

Filed:

Jul 10, 2003

Appl. No.:

10/617971

Inventors:

Sheung Hee Park - Pleasanton CA, US
Wing Han Leung - Sunnyvale CA, US
Richard M. Fastow - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518518, 36518519, 36518533

Abstract:

A method of programming a memory device comprises applying a first programming voltage to one of a plurality of wordlines, corresponding to a cell to be programmed. The first programming voltage is substantially equal to the desired threshold voltage. A second programming voltage is also applied to one of a plurality of bitlines, corresponding to the cell to be programmed. The second programming voltage gradually increases from a low level toward a high level. The first programming voltage and second programming voltage are removed when the corresponding bitline current begins to decrease.

US Patent:

7283398, Oct 16, 2007

Filed:

May 4, 2004

Appl. No.:

10/838962

Inventors:

Richard Fastow - Cupertino CA, US
Takao Akaogi - Cupertino CA, US
Wing Leung - Palo Alto CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 16/06

US Classification:

36518522, 36518523, 36518502, 36518518

Abstract:

The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.

US Patent:

7319615, Jan 15, 2008

Filed:

Aug 2, 2006

Appl. No.:

11/497597

Inventors:

Gwyn Jones - Sunnyvale CA, US
Wing Leung - Palo Alto CA, US
Edward Franklin Runnion - Santa Clara CA, US
Xuguang Wang - Sunnyvale CA, US
Yi He - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 16/06

US Classification:

36518522, 36518514, 36518533

Abstract:

A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.