Wing Hing Leung

US Patent:

6937518, Aug 30, 2005

Filed:

Jul 10, 2003

Appl. No.:

10/617971

Inventors:

Sheung Hee Park - Pleasanton CA, US
Wing Han Leung - Sunnyvale CA, US
Richard M. Fastow - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518518, 36518519, 36518533

Abstract:

A method of programming a memory device comprises applying a first programming voltage to one of a plurality of wordlines, corresponding to a cell to be programmed. The first programming voltage is substantially equal to the desired threshold voltage. A second programming voltage is also applied to one of a plurality of bitlines, corresponding to the cell to be programmed. The second programming voltage gradually increases from a low level toward a high level. The first programming voltage and second programming voltage are removed when the corresponding bitline current begins to decrease.

US Patent:

7319615, Jan 15, 2008

Filed:

Aug 2, 2006

Appl. No.:

11/497597

Inventors:

Gwyn Jones - Sunnyvale CA, US
Wing Leung - Palo Alto CA, US
Edward Franklin Runnion - Santa Clara CA, US
Xuguang Wang - Sunnyvale CA, US
Yi He - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 16/06

US Classification:

36518522, 36518514, 36518533

Abstract:

A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

US Patent:

7385851, Jun 10, 2008

Filed:

Dec 22, 2006

Appl. No.:

11/615710

Inventors:

Ming Kwan - San Leandro CA, US
Wing Leung - Palo Alto CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 16/06

US Classification:

36518522, 36518517, 36518521

Abstract:

Erase verify operations as described herein can be utilized for a flash memory device having an array of memory cells. The erase verify operations employ repetitive erase verify testing to double-check previously verified bits that might otherwise relax or settle into an under-erased state. Following an initial erase verify procedure, an erase verify operation may perform a secondary erase verify procedure and apply additional erase pulses to bits that have become under-erased.

US Patent:

7561471, Jul 14, 2009

Filed:

Mar 16, 2007

Appl. No.:

11/724711

Inventors:

Xuguang Wang - Sunnyvale CA, US
Wing Leung - Palo Alto CA, US
Yi He - Fremont CA, US
Edward Franklin Runnion - Santa Clara CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 16/16

US Classification:

36518519, 36518518, 36518533, 36518529, 36518503

Abstract:

Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.