Yu H Huang

US Patent:

7211464, May 1, 2007

Filed:

Mar 17, 2005

Appl. No.:

11/082372

Inventors:

Charles M. Lieber - Lexington MA, US
Yi Cui - Union City CA, US
Xiangfeng Duan - Mountain View CA, US
Yu Huang - Cambridge MA, US

Assignee:

President & Fellows of Harvard College - Cambridge MA

International Classification:

H01L 51/40
D01C 5/00
D01F 9/12

US Classification:

438 99, 438962, 4234473, 977762, 977936, 257E29086, 257E29174, 257E51023

Abstract:

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing.

US Patent:

7254151, Aug 7, 2007

Filed:

Dec 11, 2003

Appl. No.:

10/734086

Inventors:

Charles M. Lieber - Lexington MA, US
Xiangfeng Duan - Cambridge MA, US
Yu Huang - Cambridge MA, US
Ritesh Agarwal - Cambridge MA, US

Assignee:

President & Fellows of Harvard College - Cambridge MA

International Classification:

H01S 5/00

US Classification:

372 4401, 977951, 977825

Abstract:

This invention generally relates to nanotechnology and nanoelectronics as well as associated methods and devices. In particular, the invention relates to nanoscale optical components such as electroluminescence devices (e. g. , LEDs), amplified stimulated emission devices (e. g. , lasers), waveguides, and optical cavities (e. g. , resonators). Articles and devices of a size greater than the nanoscale are also included. Such devices can be formed from nanoscale wires such as nanowires or nanotubes. In some cases, the nanoscale wire is a single crystal. In one embodiment, the nanoscale laser is constructed as a Fabry-Perot cavity, and is driven by electrical injection. Any electrical injection source may be used. For example, electrical injection may be accomplished through a crossed wire configuration, an electrode or distributed electrode configuration, or a core/shell configuration. The output wavelength can be controlled, for example, by varying the types of materials used to fabricate the device.

US Patent:

7301199, Nov 27, 2007

Filed:

Jul 16, 2002

Appl. No.:

10/196337

Inventors:

Charles M. Lieber - Lexington MA, US
Xiangfeng Duan - Somerville MA, US
Yi Cui - Union City CA, US
Yu Huang - Cambridge MA, US
Mark Gudiksen - Watertown MA, US
Lincoln J. Lauhon - Boston MA, US
Jianfang Wang - Goleta CA, US
Hongkun Park - Lexington MA, US
Qingqiao Wei - Corvallis OR, US
Wenjie Liang - Somerville MA, US
David C. Smith - Reading, GB
Deli Wang - Cambridge MA, US
Zhaohui Zhong - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 29/76
H01L 29/94
H01L 29/06

US Classification:

257327, 257 9, 977938, 977936, 977958

Abstract:

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

US Patent:

7476596, Jan 13, 2009

Filed:

Oct 4, 2006

Appl. No.:

11/543336

Inventors:

Charles M. Lieber - Lexington MA, US
Yi Cui - Union City CA, US
Xiangfeng Duan - Mountain View CA, US
Yu Huang - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 21/46

US Classification:

438458, 257E216, 977762, 977883

Abstract:

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor.

US Patent:

7595260, Sep 29, 2009

Filed:

Oct 4, 2006

Appl. No.:

11/543326

Inventors:

Charles M. Lieber - Lexington MA, US
Yi Cui - Union City CA, US
Xiangfeng Duan - Mountain View CA, US
Yu Huang - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 21/30
H01L 21/86

US Classification:

438495, 438499, 977858, 977882

Abstract:

A bulk-doped semiconductor may be at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may have a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof.

US Patent:

7666708, Feb 23, 2010

Filed:

Oct 4, 2006

Appl. No.:

11/543352

Inventors:

Charles M. Lieber - Lexington MA, US
Yi Cui - Union City CA, US
Xiangfeng Duan - Mountain View CA, US
Yu Huang - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 51/40
D01C 5/00
D01F 9/12

US Classification:

438 99, 4234473, 977762, 257E51023

Abstract:

A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal is, axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less an 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety assembling techniques may be used to fabricate devices from such a semiconductor.

US Patent:

7729884, Jun 1, 2010

Filed:

Nov 4, 2005

Appl. No.:

11/267221

Inventors:

Yu Huang - Marlborough MA, US
Janusz Rajski - West Linn OR, US

International Classification:

G06F 11/30
G06F 11/00

US Classification:

702185, 714738

Abstract:

Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received including entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.

US Patent:

7788561, Aug 31, 2010

Filed:

Aug 14, 2007

Appl. No.:

11/838858

Inventors:

Yu Huang - Marlborough MA, US
Ruifeng Guo - Portland OR, US

International Classification:

G01R 31/28

US Classification:

714729, 714 3, 714 8, 714 25, 714 30, 714 31, 714 37, 714 48, 714709, 714723, 714724, 714726, 714727, 714742, 702183, 702185, 703 13, 703 14, 703 15

Abstract:

Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.